* [PATCH 1/4] ARM: add CPU_THUMB_CAPABLE to indicate possible Thumb support
2017-02-09 12:17 [PATCH 0/4] kuser updates for ARM-only vs Thumb Russell King - ARM Linux
@ 2017-02-09 12:18 ` Russell King
2017-02-10 17:29 ` Stephen Boyd
2017-02-09 12:18 ` [PATCH 2/4] ARM: kuser: split out kuser code Russell King
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Russell King @ 2017-02-09 12:18 UTC (permalink / raw)
To: linux-arm-kernel
Clean up arch/arm/mm/Kconfig a little to provide a symbol which
indicates whether the CPU may support the Thumb instruction set. This
gets rid of the growing dependencies on ARM_THUMB, and also gives us a
useful Kconfig symbol for choosing the kuser code.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/mm/Kconfig | 31 ++++++++++++++++++++++++++-----
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index f68e8ec29447..d6552ab45ed1 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -29,6 +29,7 @@ config CPU_ARM720T
select CPU_COPY_V4WT if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WT if MMU
help
A 32-bit RISC processor with 8kByte Cache, Write Buffer and
@@ -46,6 +47,7 @@ config CPU_ARM740T
select CPU_CACHE_V4
select CPU_CP15_MPU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
help
A 32-bit RISC processor with 8KB cache or 4KB variants,
write buffer and MPU(Protection Unit) built around
@@ -79,6 +81,7 @@ config CPU_ARM920T
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
The ARM920T is licensed to be produced by numerous vendors,
@@ -97,6 +100,7 @@ config CPU_ARM922T
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
The ARM922T is a version of the ARM920T, but with smaller
@@ -116,6 +120,7 @@ config CPU_ARM925T
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
The ARM925T is a mix between the ARM920T and ARM926T, but with
@@ -134,6 +139,7 @@ config CPU_ARM926T
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
This is a variant of the ARM920. It has slightly different
@@ -170,6 +176,7 @@ config CPU_ARM940T
select CPU_CACHE_VIVT
select CPU_CP15_MPU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
help
ARM940T is a member of the ARM9TDMI family of general-
purpose microprocessors with MPU and separate 4KB
@@ -188,6 +195,7 @@ config CPU_ARM946E
select CPU_CACHE_VIVT
select CPU_CP15_MPU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
help
ARM946E-S is a member of the ARM9E-S family of high-
performance, 32-bit system-on-chip processor solutions.
@@ -206,6 +214,7 @@ config CPU_ARM1020
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
The ARM1020 is the 32K cached version of the ARM10 processor,
@@ -225,6 +234,7 @@ config CPU_ARM1020E
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
# ARM1022E
@@ -236,6 +246,7 @@ config CPU_ARM1022
select CPU_COPY_V4WB if MMU # can probably do better
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
The ARM1022E is an implementation of the ARMv5TE architecture
@@ -254,6 +265,7 @@ config CPU_ARM1026
select CPU_COPY_V4WB if MMU # can probably do better
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
help
The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
@@ -302,6 +314,7 @@ config CPU_XSCALE
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
# XScale Core Version 3
@@ -312,6 +325,7 @@ config CPU_XSC3
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
select IO_36
@@ -324,6 +338,7 @@ config CPU_MOHAWK
select CPU_COPY_V4WB if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V4WBI if MMU
# Feroceon
@@ -335,6 +350,7 @@ config CPU_FEROCEON
select CPU_COPY_FEROCEON if MMU
select CPU_CP15_MMU
select CPU_PABRT_LEGACY
+ select CPU_THUMB_CAPABLE
select CPU_TLB_FEROCEON if MMU
config CPU_FEROCEON_OLD_ID
@@ -367,6 +383,7 @@ config CPU_V6
select CPU_CP15_MMU
select CPU_HAS_ASID if MMU
select CPU_PABRT_V6
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V6 if MMU
# ARMv6k
@@ -381,6 +398,7 @@ config CPU_V6K
select CPU_CP15_MMU
select CPU_HAS_ASID if MMU
select CPU_PABRT_V6
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V6 if MMU
# ARMv7
@@ -396,6 +414,7 @@ config CPU_V7
select CPU_CP15_MPU if !MMU
select CPU_HAS_ASID if MMU
select CPU_PABRT_V7
+ select CPU_THUMB_CAPABLE
select CPU_TLB_V7 if MMU
# ARMv7M
@@ -410,11 +429,17 @@ config CPU_V7M
config CPU_THUMBONLY
bool
+ select CPU_THUMB_CAPABLE
# There are no CPUs available with MMU that don't implement an ARM ISA:
depends on !MMU
help
Select this if your CPU doesn't support the 32 bit ARM instructions.
+config CPU_THUMB_CAPABLE
+ bool
+ help
+ Selected this if your CPU can support Thumb mode
+
# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
@@ -655,11 +680,7 @@ config ARCH_DMA_ADDR_T_64BIT
config ARM_THUMB
bool "Support Thumb user binaries" if !CPU_THUMBONLY
- depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
- CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
- CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
- CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
- CPU_V7 || CPU_FEROCEON || CPU_V7M
+ depends on CPU_THUMB_CAPABLE
default y
help
Say Y if you want to include kernel support for running user space
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/4] ARM: kuser: split out kuser code
2017-02-09 12:17 [PATCH 0/4] kuser updates for ARM-only vs Thumb Russell King - ARM Linux
2017-02-09 12:18 ` [PATCH 1/4] ARM: add CPU_THUMB_CAPABLE to indicate possible Thumb support Russell King
@ 2017-02-09 12:18 ` Russell King
2017-02-09 12:18 ` [PATCH 3/4] ARM: kuser: simplify kuser_cmpxchg* preprocessor conditionals Russell King
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Russell King @ 2017-02-09 12:18 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/kernel/Makefile | 2 +
arch/arm/kernel/entry-armv.S | 198 -------------------------------------------
arch/arm/kernel/kuser.S | 197 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 199 insertions(+), 198 deletions(-)
create mode 100644 arch/arm/kernel/kuser.S
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index f7751cb71fb1..a7c21ce534e3 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -30,6 +30,8 @@ else
obj-y += entry-armv.o
endif
+obj-$(CONFIG_KUSER_HELPERS) += kuser.o
+
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ISA_DMA_API) += dma.o
obj-$(CONFIG_FIQ) += fiq.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 9f157e7c51e7..3acc6e6b948c 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -819,204 +819,6 @@ ENTRY(__switch_to)
UNWIND(.fnend )
ENDPROC(__switch_to)
- __INIT
-
-/*
- * User helpers.
- *
- * Each segment is 32-byte aligned and will be moved to the top of the high
- * vector page. New segments (if ever needed) must be added in front of
- * existing ones. This mechanism should be used only for things that are
- * really small and justified, and not be abused freely.
- *
- * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
- */
- THUMB( .arm )
-
- .macro usr_ret, reg
-#ifdef CONFIG_ARM_THUMB
- bx \reg
-#else
- ret \reg
-#endif
- .endm
-
- .macro kuser_pad, sym, size
- .if (. - \sym) & 3
- .rept 4 - (. - \sym) & 3
- .byte 0
- .endr
- .endif
- .rept (\size - (. - \sym)) / 4
- .word 0xe7fddef1
- .endr
- .endm
-
-#ifdef CONFIG_KUSER_HELPERS
- .align 5
- .globl __kuser_helper_start
-__kuser_helper_start:
-
-/*
- * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
- * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
- */
-
-__kuser_cmpxchg64: @ 0xffff0f60
-
-#if defined(CONFIG_CPU_32v6K)
-
- stmfd sp!, {r4, r5, r6, r7}
- ldrd r4, r5, [r0] @ load old val
- ldrd r6, r7, [r1] @ load new val
- smp_dmb arm
-1: ldrexd r0, r1, [r2] @ load current val
- eors r3, r0, r4 @ compare with oldval (1)
- eoreqs r3, r1, r5 @ compare with oldval (2)
- strexdeq r3, r6, r7, [r2] @ store newval if eq
- teqeq r3, #1 @ success?
- beq 1b @ if no then retry
- smp_dmb arm
- rsbs r0, r3, #0 @ set returned val and C flag
- ldmfd sp!, {r4, r5, r6, r7}
- usr_ret lr
-
-#elif !defined(CONFIG_SMP)
-
-#ifdef CONFIG_MMU
-
- /*
- * The only thing that can break atomicity in this cmpxchg64
- * implementation is either an IRQ or a data abort exception
- * causing another process/thread to be scheduled in the middle of
- * the critical sequence. The same strategy as for cmpxchg is used.
- */
- stmfd sp!, {r4, r5, r6, lr}
- ldmia r0, {r4, r5} @ load old val
- ldmia r1, {r6, lr} @ load new val
-1: ldmia r2, {r0, r1} @ load current val
- eors r3, r0, r4 @ compare with oldval (1)
- eoreqs r3, r1, r5 @ compare with oldval (2)
-2: stmeqia r2, {r6, lr} @ store newval if eq
- rsbs r0, r3, #0 @ set return val and C flag
- ldmfd sp!, {r4, r5, r6, pc}
-
- .text
-kuser_cmpxchg64_fixup:
- @ Called from kuser_cmpxchg_fixup.
- @ r4 = address of interrupted insn (must be preserved).
- @ sp = saved regs. r7 and r8 are clobbered.
- @ 1b = first critical insn, 2b = last critical insn.
- @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
- mov r7, #0xffff0fff
- sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
- subs r8, r4, r7
- rsbcss r8, r8, #(2b - 1b)
- strcs r7, [sp, #S_PC]
-#if __LINUX_ARM_ARCH__ < 6
- bcc kuser_cmpxchg32_fixup
-#endif
- ret lr
- .previous
-
-#else
-#warning "NPTL on non MMU needs fixing"
- mov r0, #-1
- adds r0, r0, #0
- usr_ret lr
-#endif
-
-#else
-#error "incoherent kernel configuration"
-#endif
-
- kuser_pad __kuser_cmpxchg64, 64
-
-__kuser_memory_barrier: @ 0xffff0fa0
- smp_dmb arm
- usr_ret lr
-
- kuser_pad __kuser_memory_barrier, 32
-
-__kuser_cmpxchg: @ 0xffff0fc0
-
-#if __LINUX_ARM_ARCH__ < 6
-
-#ifdef CONFIG_MMU
-
- /*
- * The only thing that can break atomicity in this cmpxchg
- * implementation is either an IRQ or a data abort exception
- * causing another process/thread to be scheduled in the middle
- * of the critical sequence. To prevent this, code is added to
- * the IRQ and data abort exception handlers to set the pc back
- * to the beginning of the critical section if it is found to be
- * within that critical section (see kuser_cmpxchg_fixup).
- */
-1: ldr r3, [r2] @ load current val
- subs r3, r3, r0 @ compare with oldval
-2: streq r1, [r2] @ store newval if eq
- rsbs r0, r3, #0 @ set return val and C flag
- usr_ret lr
-
- .text
-kuser_cmpxchg32_fixup:
- @ Called from kuser_cmpxchg_check macro.
- @ r4 = address of interrupted insn (must be preserved).
- @ sp = saved regs. r7 and r8 are clobbered.
- @ 1b = first critical insn, 2b = last critical insn.
- @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
- mov r7, #0xffff0fff
- sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
- subs r8, r4, r7
- rsbcss r8, r8, #(2b - 1b)
- strcs r7, [sp, #S_PC]
- ret lr
- .previous
-
-#else
-#warning "NPTL on non MMU needs fixing"
- mov r0, #-1
- adds r0, r0, #0
- usr_ret lr
-#endif
-
-#else
-
- smp_dmb arm
-1: ldrex r3, [r2]
- subs r3, r3, r0
- strexeq r3, r1, [r2]
- teqeq r3, #1
- beq 1b
- rsbs r0, r3, #0
- /* beware -- each __kuser slot must be 8 instructions max */
- ALT_SMP(b __kuser_memory_barrier)
- ALT_UP(usr_ret lr)
-
-#endif
-
- kuser_pad __kuser_cmpxchg, 32
-
-__kuser_get_tls: @ 0xffff0fe0
- ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
- usr_ret lr
- mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
- kuser_pad __kuser_get_tls, 16
- .rep 3
- .word 0 @ 0xffff0ff0 software TLS value, then
- .endr @ pad up to __kuser_helper_version
-
-__kuser_helper_version: @ 0xffff0ffc
- .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
-
- .globl __kuser_helper_end
-__kuser_helper_end:
-
-#endif
-
- THUMB( .thumb )
-
/*
* Vector stubs.
*
diff --git a/arch/arm/kernel/kuser.S b/arch/arm/kernel/kuser.S
new file mode 100644
index 000000000000..5d2a2784ed09
--- /dev/null
+++ b/arch/arm/kernel/kuser.S
@@ -0,0 +1,197 @@
+#include <linux/init.h>
+
+#include <asm/assembler.h>
+
+ __INIT
+
+/*
+ * User helpers.
+ *
+ * Each segment is 32-byte aligned and will be moved to the top of the high
+ * vector page. New segments (if ever needed) must be added in front of
+ * existing ones. This mechanism should be used only for things that are
+ * really small and justified, and not be abused freely.
+ *
+ * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
+ */
+ THUMB( .arm )
+
+ .macro usr_ret, reg
+#ifdef CONFIG_ARM_THUMB
+ bx \reg
+#else
+ ret \reg
+#endif
+ .endm
+
+ .macro kuser_pad, sym, size
+ .if (. - \sym) & 3
+ .rept 4 - (. - \sym) & 3
+ .byte 0
+ .endr
+ .endif
+ .rept (\size - (. - \sym)) / 4
+ .word 0xe7fddef1
+ .endr
+ .endm
+
+ .align 5
+ .globl __kuser_helper_start
+__kuser_helper_start:
+
+/*
+ * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
+ * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
+ */
+
+__kuser_cmpxchg64: @ 0xffff0f60
+
+#if defined(CONFIG_CPU_32v6K)
+
+ stmfd sp!, {r4, r5, r6, r7}
+ ldrd r4, r5, [r0] @ load old val
+ ldrd r6, r7, [r1] @ load new val
+ smp_dmb arm
+1: ldrexd r0, r1, [r2] @ load current val
+ eors r3, r0, r4 @ compare with oldval (1)
+ eoreqs r3, r1, r5 @ compare with oldval (2)
+ strexdeq r3, r6, r7, [r2] @ store newval if eq
+ teqeq r3, #1 @ success?
+ beq 1b @ if no then retry
+ smp_dmb arm
+ rsbs r0, r3, #0 @ set returned val and C flag
+ ldmfd sp!, {r4, r5, r6, r7}
+ usr_ret lr
+
+#elif !defined(CONFIG_SMP)
+
+#ifdef CONFIG_MMU
+
+ /*
+ * The only thing that can break atomicity in this cmpxchg64
+ * implementation is either an IRQ or a data abort exception
+ * causing another process/thread to be scheduled in the middle of
+ * the critical sequence. The same strategy as for cmpxchg is used.
+ */
+ stmfd sp!, {r4, r5, r6, lr}
+ ldmia r0, {r4, r5} @ load old val
+ ldmia r1, {r6, lr} @ load new val
+1: ldmia r2, {r0, r1} @ load current val
+ eors r3, r0, r4 @ compare with oldval (1)
+ eoreqs r3, r1, r5 @ compare with oldval (2)
+2: stmeqia r2, {r6, lr} @ store newval if eq
+ rsbs r0, r3, #0 @ set return val and C flag
+ ldmfd sp!, {r4, r5, r6, pc}
+
+ .text
+ .globl kuser_cmpxchg64_fixup
+kuser_cmpxchg64_fixup:
+ @ Called from kuser_cmpxchg_check macro.
+ @ r4 = address of interrupted insn (must be preserved).
+ @ sp = saved regs. r7 and r8 are clobbered.
+ @ 1b = first critical insn, 2b = last critical insn.
+ @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
+ mov r7, #0xffff0fff
+ sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
+ subs r8, r4, r7
+ rsbcss r8, r8, #(2b - 1b)
+ strcs r7, [sp, #S_PC]
+#if __LINUX_ARM_ARCH__ < 6
+ bcc kuser_cmpxchg32_fixup
+#endif
+ ret lr
+ .previous
+
+#else
+#warning "NPTL on non MMU needs fixing"
+ mov r0, #-1
+ adds r0, r0, #0
+ usr_ret lr
+#endif
+
+#else
+#error "incoherent kernel configuration"
+#endif
+
+ kuser_pad __kuser_cmpxchg64, 64
+
+__kuser_memory_barrier: @ 0xffff0fa0
+ smp_dmb arm
+ usr_ret lr
+
+ kuser_pad __kuser_memory_barrier, 32
+
+__kuser_cmpxchg: @ 0xffff0fc0
+
+#if __LINUX_ARM_ARCH__ < 6
+
+#ifdef CONFIG_MMU
+
+ /*
+ * The only thing that can break atomicity in this cmpxchg
+ * implementation is either an IRQ or a data abort exception
+ * causing another process/thread to be scheduled in the middle
+ * of the critical sequence. To prevent this, code is added to
+ * the IRQ and data abort exception handlers to set the pc back
+ * to the beginning of the critical section if it is found to be
+ * within that critical section (see kuser_cmpxchg_check).
+ */
+1: ldr r3, [r2] @ load current val
+ subs r3, r3, r0 @ compare with oldval
+2: streq r1, [r2] @ store newval if eq
+ rsbs r0, r3, #0 @ set return val and C flag
+ usr_ret lr
+
+ .text
+kuser_cmpxchg32_fixup:
+ @ Called from kuser_cmpxchg64_fixup above via kuser_cmpxchg_check macro.
+ @ r4 = address of interrupted insn (must be preserved).
+ @ sp = saved regs. r7 and r8 are clobbered.
+ @ 1b = first critical insn, 2b = last critical insn.
+ @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
+ mov r7, #0xffff0fff
+ sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
+ subs r8, r4, r7
+ rsbcss r8, r8, #(2b - 1b)
+ strcs r7, [sp, #S_PC]
+ ret lr
+ .previous
+
+#else
+#warning "NPTL on non MMU needs fixing"
+ mov r0, #-1
+ adds r0, r0, #0
+ usr_ret lr
+#endif
+
+#else
+
+ smp_dmb arm
+1: ldrex r3, [r2]
+ subs r3, r3, r0
+ strexeq r3, r1, [r2]
+ teqeq r3, #1
+ beq 1b
+ rsbs r0, r3, #0
+ /* beware -- each __kuser slot must be 8 instructions max */
+ ALT_SMP(b __kuser_memory_barrier)
+ ALT_UP(usr_ret lr)
+
+#endif
+
+ kuser_pad __kuser_cmpxchg, 32
+
+__kuser_get_tls: @ 0xffff0fe0
+ ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
+ usr_ret lr
+ mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
+ kuser_pad __kuser_get_tls, 16
+ .rep 3
+ .word 0 @ 0xffff0ff0 software TLS value, then
+ .endr @ pad up to __kuser_helper_version
+
+__kuser_helper_version: @ 0xffff0ffc
+ .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
+
+ .globl __kuser_helper_end
+__kuser_helper_end:
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/4] ARM: kuser: split the kuser support for Thumb-capable and ARM-only
2017-02-09 12:17 [PATCH 0/4] kuser updates for ARM-only vs Thumb Russell King - ARM Linux
` (2 preceding siblings ...)
2017-02-09 12:18 ` [PATCH 3/4] ARM: kuser: simplify kuser_cmpxchg* preprocessor conditionals Russell King
@ 2017-02-09 12:18 ` Russell King
2017-02-09 19:25 ` Nicolas Pitre
2017-02-20 17:06 ` [PATCH 0/4] kuser updates for ARM-only vs Thumb Martin Kaiser
4 siblings, 1 reply; 9+ messages in thread
From: Russell King @ 2017-02-09 12:18 UTC (permalink / raw)
To: linux-arm-kernel
We need to build the kuser code differently for Thumb-capable CPUs vs
ARM-capable CPUs. However, we do not want to require two different
kernel configurations to support this - we want to choose between the
two variants at run time.
In order to achieve this, we build the kuser.S code differently, and
choose to copy the appropriate version into the kuser page.
However, there is a twist - there are fixups within this code that are
needed for supporting some of the operations, and these end up
duplicated, which leads to a linker error. Thankfully, the fixups
result in identical code, so we choose to drop one set of these.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/kernel/Makefile | 10 +++++++++-
arch/arm/kernel/kuser-t.S | 13 ++++++++++++
arch/arm/kernel/kuser-v4.S | 11 +++++++++++
arch/arm/kernel/kuser.S | 49 +++++++++++++++++++++++++---------------------
arch/arm/kernel/traps.c | 37 ++++++++++++++++++++++++++++++----
5 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/kernel/kuser-t.S
create mode 100644 arch/arm/kernel/kuser-v4.S
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index a7c21ce534e3..2f3683723157 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -30,7 +30,15 @@ else
obj-y += entry-armv.o
endif
-obj-$(CONFIG_KUSER_HELPERS) += kuser.o
+# Build non-Thumb variant for non-Thumb CPUs
+kuser-$(CONFIG_CPU_32v3) += kuser-v4.o
+kuser-$(CONFIG_CPU_32v4) += kuser-v4.o
+
+# Always build kuser-t for an arch that includes Thumb support
+AFLAGS_kuser-t.o := -march=armv7-a
+kuser-$(CONFIG_CPU_THUMB_CAPABLE) += kuser-t.o
+
+obj-$(CONFIG_KUSER_HELPERS) += $(kuser-y)
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ISA_DMA_API) += dma.o
diff --git a/arch/arm/kernel/kuser-t.S b/arch/arm/kernel/kuser-t.S
new file mode 100644
index 000000000000..59eebf27a462
--- /dev/null
+++ b/arch/arm/kernel/kuser-t.S
@@ -0,0 +1,13 @@
+#include <asm/assembler.h>
+
+#if !(defined(CONFIG_CPU_32v3) || defined(CONFIG_CPU_32v4))
+#define GENERATE_FIXUPS
+#endif
+
+#define SYM(x) x##_thumb
+
+ .macro usr_ret, reg
+ bx \reg
+ .endm
+
+#include "kuser.S"
diff --git a/arch/arm/kernel/kuser-v4.S b/arch/arm/kernel/kuser-v4.S
new file mode 100644
index 000000000000..5a357fa33521
--- /dev/null
+++ b/arch/arm/kernel/kuser-v4.S
@@ -0,0 +1,11 @@
+#include <asm/assembler.h>
+
+#define GENERATE_FIXUPS
+
+#define SYM(x) x##_v4
+
+ .macro usr_ret, reg
+ mov pc, \reg
+ .endm
+
+#include "kuser.S"
diff --git a/arch/arm/kernel/kuser.S b/arch/arm/kernel/kuser.S
index d7081a4761fe..1b8d87776e1d 100644
--- a/arch/arm/kernel/kuser.S
+++ b/arch/arm/kernel/kuser.S
@@ -1,11 +1,19 @@
#include <linux/init.h>
-#include <asm/assembler.h>
-
#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_32v6K)
#error "incoherent kernel configuration"
#endif
+#ifdef GENERATE_FIXUPS
+/*
+ * The .text section in this file is used for fixups of the various
+ * helpers. Do not place anything else in the .text section within
+ * this file.
+ */
+ .globl kuser_cmpxchg64_fixup
+kuser_cmpxchg64_fixup:
+#endif
+
__INIT
/*
@@ -20,14 +28,6 @@
*/
THUMB( .arm )
- .macro usr_ret, reg
-#ifdef CONFIG_ARM_THUMB
- bx \reg
-#else
- ret \reg
-#endif
- .endm
-
.macro kuser_pad, sym, size
.if (. - \sym) & 3
.rept 4 - (. - \sym) & 3
@@ -40,8 +40,8 @@
.endm
.align 5
- .globl __kuser_helper_start
-__kuser_helper_start:
+ .globl SYM(__kuser_helper_start)
+SYM(__kuser_helper_start):
/*
* Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
@@ -85,9 +85,8 @@ __kuser_cmpxchg64: @ 0xffff0f60
rsbs r0, r3, #0 @ set return val and C flag
ldmfd sp!, {r4, r5, r6, pc}
+#ifdef GENERATE_FIXUPS
.text
- .globl kuser_cmpxchg64_fixup
-kuser_cmpxchg64_fixup:
@ Called from kuser_cmpxchg_check macro.
@ r4 = address of interrupted insn (must be preserved).
@ sp = saved regs. r7 and r8 are clobbered.
@@ -98,11 +97,9 @@ __kuser_cmpxchg64: @ 0xffff0f60
subs r8, r4, r7
rsbcss r8, r8, #(2b - 1b)
strcs r7, [sp, #S_PC]
-#if __LINUX_ARM_ARCH__ < 6
- bcc kuser_cmpxchg32_fixup
-#endif
- ret lr
+ retcs lr
.previous
+#endif
#else
#warning "NPTL on non MMU needs fixing"
@@ -151,6 +148,7 @@ __kuser_cmpxchg: @ 0xffff0fc0
rsbs r0, r3, #0 @ set return val and C flag
usr_ret lr
+#ifdef GENERATE_FIXUPS
.text
kuser_cmpxchg32_fixup:
@ Called from kuser_cmpxchg64_fixup above via kuser_cmpxchg_check macro.
@@ -163,8 +161,9 @@ __kuser_cmpxchg: @ 0xffff0fc0
subs r8, r4, r7
rsbcss r8, r8, #(2b - 1b)
strcs r7, [sp, #S_PC]
- ret lr
+ retcs lr
.previous
+#endif
#else
#warning "NPTL on non MMU needs fixing"
@@ -185,7 +184,13 @@ __kuser_get_tls: @ 0xffff0fe0
.endr @ pad up to __kuser_helper_version
__kuser_helper_version: @ 0xffff0ffc
- .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
+ .word ((SYM(__kuser_helper_end) - SYM(__kuser_helper_start)) >> 5)
+
+ .globl SYM(__kuser_helper_end)
+SYM(__kuser_helper_end):
- .globl __kuser_helper_end
-__kuser_helper_end:
+#ifdef GENERATE_FIXUPS
+ .text
+ /* Kuser fixups finishing instruction */
+ ret lr
+#endif
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index ff2ae872d555..1a7aa28a0074 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -792,12 +792,41 @@ void __init trap_init(void)
}
#ifdef CONFIG_KUSER_HELPERS
-static void __init kuser_init(void *vectors)
+#ifdef CONFIG_CPU_THUMB_CAPABLE
+static void __init kuser_thumb_init(void *vectors)
+{
+ extern char __kuser_helper_start_thumb[], __kuser_helper_end_thumb[];
+ int kuser_sz = __kuser_helper_end_thumb - __kuser_helper_start_thumb;
+
+ memcpy(vectors + 0x1000 - kuser_sz, __kuser_helper_start_thumb,
+ kuser_sz);
+}
+#else
+static void __init kuser_thumb_init(void *vectors)
+{
+}
+#endif
+
+#if defined(CONFIG_CPU_32v3) || defined(CONFIG_CPU_32v4)
+static void __init kuser_v4_init(void *vectors)
{
- extern char __kuser_helper_start[], __kuser_helper_end[];
- int kuser_sz = __kuser_helper_end - __kuser_helper_start;
+ extern char __kuser_helper_start_v4[], __kuser_helper_end_v4[];
+ int kuser_sz = __kuser_helper_end_v4 - __kuser_helper_start_v4;
- memcpy(vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
+ memcpy(vectors + 0x1000 - kuser_sz, __kuser_helper_start_v4, kuser_sz);
+}
+#else
+static void __init kuser_v4_init(void *vectors)
+{
+}
+#endif
+
+static void __init kuser_init(void *vectors)
+{
+ if (!(elf_hwcap & HWCAP_THUMB))
+ kuser_v4_init(vectors);
+ else
+ kuser_thumb_init(vectors);
/*
* vectors + 0xfe0 = __kuser_get_tls
--
2.7.4
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