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From: cdall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC 28/55] KVM: arm/arm64: Prepare vgic state for the nested VM
Date: Wed, 22 Feb 2017 14:12:46 +0100	[thread overview]
Message-ID: <20170222131246.GP26976@cbox> (raw)
In-Reply-To: <1483943091-1364-29-git-send-email-jintack@cs.columbia.edu>

On Mon, Jan 09, 2017 at 01:24:24AM -0500, Jintack Lim wrote:
> When entering a nested VM, we set up the hypervisor control interface
> based on what the guest hypervisor has set. Especially, we investigate
> each list register written by the guest hypervisor whether HW bit is
> set.  If so, we translate hw irq number from the guest's point of view
> to the real hardware irq number if there is a mapping.

Does that really always work?

Are there not some assumptions about the virtual device that the guest
hypervisor is mapping the virtual IRQ to also exists as an equivalent
device with some connected state on the host?

Thanks,
-Christoffer

> 
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
> ---
>  arch/arm/include/asm/kvm_emulate.h   |  5 ++
>  arch/arm64/include/asm/kvm_emulate.h |  5 ++
>  arch/arm64/kvm/context.c             |  4 ++
>  include/kvm/arm_vgic.h               |  8 +++
>  virt/kvm/arm/vgic/vgic-init.c        |  3 ++
>  virt/kvm/arm/vgic/vgic-v2-nested.c   | 99 ++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic.h             | 11 ++++
>  7 files changed, 135 insertions(+)
> 
> diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
> index 0fa2f5a..05d5906 100644
> --- a/arch/arm/include/asm/kvm_emulate.h
> +++ b/arch/arm/include/asm/kvm_emulate.h
> @@ -101,6 +101,11 @@ static inline bool vcpu_mode_el2(const struct kvm_vcpu *vcpu)
>  	return false;
>  }
>  
> +static inline bool vcpu_el2_imo_is_set(const struct kvm_vcpu *vcpu)
> +{
> +	return false;
> +}
> +
>  static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
>  {
>  	return &vcpu->arch.ctxt.gp_regs.usr_regs.ARM_pc;
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index 0987ee4..a9c993f 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -178,6 +178,11 @@ static inline bool vcpu_mode_el2(const struct kvm_vcpu *vcpu)
>  	return mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t;
>  }
>  
> +static inline bool vcpu_el2_imo_is_set(const struct kvm_vcpu *vcpu)
> +{
> +	return (vcpu_el2_reg(vcpu, HCR_EL2) & HCR_IMO);
> +}
> +
>  static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
>  {
>  	return vcpu->arch.fault.esr_el2;
> diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c
> index 0025dd9..7a94c9d 100644
> --- a/arch/arm64/kvm/context.c
> +++ b/arch/arm64/kvm/context.c
> @@ -161,6 +161,8 @@ void kvm_arm_setup_shadow_state(struct kvm_vcpu *vcpu)
>  		ctxt->hw_sys_regs = ctxt->sys_regs;
>  		ctxt->hw_sp_el1 = ctxt->gp_regs.sp_el1;
>  	}
> +
> +	vgic_v2_setup_shadow_state(vcpu);
>  }
>  
>  /**
> @@ -179,6 +181,8 @@ void kvm_arm_restore_shadow_state(struct kvm_vcpu *vcpu)
>  		*vcpu_cpsr(vcpu) = ctxt->hw_pstate;
>  		ctxt->gp_regs.sp_el1 = ctxt->hw_sp_el1;
>  	}
> +
> +	vgic_v2_restore_shadow_state(vcpu);
>  }
>  
>  void kvm_arm_init_cpu_context(kvm_cpu_context_t *cpu_ctxt)
> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
> index 9a9cb27..484f6b1 100644
> --- a/include/kvm/arm_vgic.h
> +++ b/include/kvm/arm_vgic.h
> @@ -312,6 +312,14 @@ int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
>  
>  int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
>  
> +#ifdef CONFIG_KVM_ARM_NESTED_HYP
> +void vgic_v2_setup_shadow_state(struct kvm_vcpu *vcpu);
> +void vgic_v2_restore_shadow_state(struct kvm_vcpu *vcpu);
> +#else
> +static inline void vgic_v2_setup_shadow_state(struct kvm_vcpu *vcpu) { }
> +static inline void vgic_v2_restore_shadow_state(struct kvm_vcpu *vcpu) { }
> +#endif
> +
>  #define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
>  #define vgic_initialized(k)	((k)->arch.vgic.initialized)
>  #define vgic_ready(k)		((k)->arch.vgic.ready)
> diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c
> index 8cebfbc..06ab8a5 100644
> --- a/virt/kvm/arm/vgic/vgic-init.c
> +++ b/virt/kvm/arm/vgic/vgic-init.c
> @@ -216,6 +216,9 @@ static void kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
>  			irq->config = VGIC_CONFIG_LEVEL;
>  		}
>  	}
> +
> +	vgic_init_nested(vcpu);
> +
>  	if (kvm_vgic_global_state.type == VGIC_V2)
>  		vgic_v2_enable(vcpu);
>  	else
> diff --git a/virt/kvm/arm/vgic/vgic-v2-nested.c b/virt/kvm/arm/vgic/vgic-v2-nested.c
> index b13128e..a992da5 100644
> --- a/virt/kvm/arm/vgic/vgic-v2-nested.c
> +++ b/virt/kvm/arm/vgic/vgic-v2-nested.c
> @@ -205,3 +205,102 @@ static void vgic_mmio_write_v2_gich(struct kvm_vcpu *vcpu,
>  		vgic_mmio_read_v2_gich, vgic_mmio_write_v2_gich,
>  		4 * VGIC_V2_MAX_LRS, VGIC_ACCESS_32bit),
>  };
> +
> +/*
> + * For LRs which have HW bit set such as timer interrupts, we modify them to
> + * have the host hardware interrupt number instead of the virtual one programmed
> + * by the guest hypervisor.
> + */
> +static void vgic_v2_create_shadow_lr(struct kvm_vcpu *vcpu)
> +{
> +	int i;
> +	struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu);
> +	struct vgic_v2_cpu_if *s_cpu_if = vcpu_shadow_if(vcpu);
> +	struct vgic_irq *irq;
> +
> +	int nr_lr = kvm_vgic_global_state.nr_lr;
> +
> +	for (i = 0; i < nr_lr; i++) {
> +		u32 lr = cpu_if->vgic_lr[i];
> +		int l1_irq;
> +
> +		if (!(lr & GICH_LR_HW))
> +			goto next;
> +
> +		/* We have the HW bit set */
> +		l1_irq = (lr & GICH_LR_PHYSID_CPUID) >>
> +			GICH_LR_PHYSID_CPUID_SHIFT;
> +		irq = vgic_get_irq(vcpu->kvm, vcpu, l1_irq);
> +
> +		if (!irq->hw) {
> +			/* There was no real mapping, so nuke the HW bit */
> +			lr &= ~GICH_LR_HW;
> +			vgic_put_irq(vcpu->kvm, irq);
> +			goto next;
> +		}
> +
> +		/* Translate the virtual mapping to the real one */
> +		lr &= ~GICH_LR_EOI;
> +		lr &= ~GICH_LR_PHYSID_CPUID;
> +		lr |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
> +		vgic_put_irq(vcpu->kvm, irq);
> +
> +next:
> +		s_cpu_if->vgic_lr[i] = lr;
> +	}
> +}
> +
> +/*
> + * Change the shadow HWIRQ field back to the virtual value before copying over
> + * the entire shadow struct to the nested state.
> + */
> +static void vgic_v2_restore_shadow_lr(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_v2_cpu_if *cpu_if = vcpu_nested_if(vcpu);
> +	struct vgic_v2_cpu_if *s_cpu_if = vcpu_shadow_if(vcpu);
> +	int nr_lr = kvm_vgic_global_state.nr_lr;
> +	int lr;
> +
> +	for (lr = 0; lr < nr_lr; lr++) {
> +		s_cpu_if->vgic_lr[lr] &= ~GICH_LR_PHYSID_CPUID;
> +		s_cpu_if->vgic_lr[lr] |= cpu_if->vgic_lr[lr] &
> +			GICH_LR_PHYSID_CPUID;
> +	}
> +}
> +
> +void vgic_v2_setup_shadow_state(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_v2_cpu_if *cpu_if;
> +
> +	if (vcpu_el2_imo_is_set(vcpu) && !vcpu_mode_el2(vcpu)) {
> +		vgic_cpu->shadow_vgic_v2 = vgic_cpu->nested_vgic_v2;
> +		vgic_v2_create_shadow_lr(vcpu);
> +		cpu_if = vcpu_shadow_if(vcpu);
> +	} else {
> +		cpu_if = &vgic_cpu->vgic_v2;
> +	}
> +
> +	vgic_cpu->hw_v2_cpu_if = cpu_if;
> +}
> +
> +void vgic_v2_restore_shadow_state(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +
> +	/* Not using shadow state: Nothing to do... */
> +	if (vgic_cpu->hw_v2_cpu_if == &vgic_cpu->vgic_v2)
> +		return;
> +
> +	/*
> +	 * Translate the shadow state HW fields back to the virtual ones
> +	 * before copying the shadow struct back to the nested one.
> +	 */
> +	vgic_v2_restore_shadow_lr(vcpu);
> +	vgic_cpu->nested_vgic_v2 = vgic_cpu->shadow_vgic_v2;
> +}
> +
> +void vgic_init_nested(struct kvm_vcpu *vcpu)
> +{
> +	vgic_v2_setup_shadow_state(vcpu);
> +}
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index 9d9e014..2aef680 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -120,4 +120,15 @@ static inline int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
>  int vgic_lazy_init(struct kvm *kvm);
>  int vgic_init(struct kvm *kvm);
>  
> +#ifdef CONFIG_KVM_ARM_NESTED_HYP
> +void vgic_init_nested(struct kvm_vcpu *vcpu);
> +#else
> +static inline void vgic_init_nested(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +
> +	vgic_cpu->hw_v2_cpu_if = &vgic_cpu->vgic_v2;
> +}
> +#endif
> +
>  #endif
> -- 
> 1.9.1
> 
> 

  reply	other threads:[~2017-02-22 13:12 UTC|newest]

Thread overview: 111+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-09  6:23 [RFC 00/55] Nested Virtualization on KVM/ARM Jintack Lim
2017-01-09  6:23 ` [RFC 01/55] arm64: Add missing TCR hw defines Jintack Lim
2017-01-09  6:23 ` [RFC 02/55] KVM: arm64: Add nesting config option Jintack Lim
2017-01-09  6:23 ` [RFC 03/55] KVM: arm64: Add KVM nesting feature Jintack Lim
2017-01-09  6:24 ` [RFC 04/55] KVM: arm64: Allow userspace to set PSR_MODE_EL2x Jintack Lim
2017-01-09  6:24 ` [RFC 05/55] KVM: arm64: Add vcpu_mode_el2 primitive to support nesting Jintack Lim
2017-01-09  6:24 ` [RFC 06/55] KVM: arm64: Add EL2 execution context for nesting Jintack Lim
2017-02-22 11:10   ` Christoffer Dall
2017-06-26 14:33     ` Jintack Lim
2017-07-03  9:03       ` Christoffer Dall
2017-07-03  9:32         ` Marc Zyngier
2017-07-03  9:54           ` Christoffer Dall
2017-07-03 14:44             ` Jintack Lim
2017-07-03 15:30               ` Christoffer Dall
2017-01-09  6:24 ` [RFC 07/55] KVM: arm/arm64: Add virtual EL2 state emulation framework Jintack Lim
2017-02-22 11:12   ` Christoffer Dall
2017-06-01 20:05   ` Bandan Das
2017-06-02 11:51     ` Christoffer Dall
2017-06-02 17:36       ` Bandan Das
2017-06-02 19:06         ` Christoffer Dall
2017-06-02 19:25           ` Bandan Das
2017-01-09  6:24 ` [RFC 08/55] KVM: arm64: Set virtual EL2 context depending on the guest exception level Jintack Lim
2017-02-22 11:14   ` Christoffer Dall
2017-06-01 20:22   ` Bandan Das
2017-06-02  8:48     ` Marc Zyngier
2017-01-09  6:24 ` [RFC 09/55] KVM: arm64: Set shadow EL1 registers for virtual EL2 execution Jintack Lim
2017-02-22 11:19   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 10/55] KVM: arm64: Synchronize EL1 system registers on virtual EL2 entry and exit Jintack Lim
2017-06-06 20:16   ` Bandan Das
2017-06-07  4:26     ` Jintack Lim
2017-01-09  6:24 ` [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor Jintack Lim
2017-02-22 11:28   ` Christoffer Dall
2017-06-06 20:21   ` Bandan Das
2017-06-06 20:38     ` Jintack Lim
2017-06-06 22:07       ` Bandan Das
2017-06-06 23:16         ` Jintack Lim
2017-06-07 17:21           ` Bandan Das
2017-01-09  6:24 ` [RFC 12/55] KVM: arm64: Handle EL2 register access traps Jintack Lim
2017-02-22 11:30   ` Christoffer Dall
2017-02-22 11:31   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 13/55] KVM: arm64: Handle eret instruction traps Jintack Lim
2017-01-09  6:24 ` [RFC 14/55] KVM: arm64: Take account of system " Jintack Lim
2017-02-22 11:34   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 15/55] KVM: arm64: Trap EL1 VM register accesses in virtual EL2 Jintack Lim
2017-01-09  6:24 ` [RFC 16/55] KVM: arm64: Forward VM reg traps to the guest hypervisor Jintack Lim
2017-02-22 11:39   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 17/55] KVM: arm64: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 in virtual EL2 Jintack Lim
2017-02-22 11:40   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 18/55] KVM: arm64: Forward traps due to HCR_EL2.NV1 bit to the guest hypervisor Jintack Lim
2017-02-22 11:41   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 19/55] KVM: arm64: Trap CPACR_EL1 access in virtual EL2 Jintack Lim
2017-01-09  6:24 ` [RFC 20/55] KVM: arm64: Forward CPACR_EL1 traps to the guest hypervisor Jintack Lim
2017-01-09  6:24 ` [RFC 21/55] KVM: arm64: Forward HVC instruction " Jintack Lim
2017-02-22 11:47   ` Christoffer Dall
2017-06-26 15:21     ` Jintack Lim
2017-07-03  9:08       ` Christoffer Dall
2017-07-03  9:31         ` Andrew Jones
2017-07-03  9:51           ` Christoffer Dall
2017-07-03 12:03             ` Will Deacon
2017-07-03 12:35               ` Marc Zyngier
2017-07-03 13:29         ` Jintack Lim
2017-01-09  6:24 ` [RFC 22/55] KVM: arm64: Handle PSCI call from the guest Jintack Lim
2017-01-09  6:24 ` [RFC 23/55] KVM: arm64: Forward WFX to the guest hypervisor Jintack Lim
2017-01-09  6:24 ` [RFC 24/55] KVM: arm64: Forward FP exceptions " Jintack Lim
2017-01-09  6:24 ` [RFC 25/55] KVM: arm/arm64: Let vcpu thread modify its own active state Jintack Lim
2017-02-22 12:27   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 26/55] KVM: arm/arm64: Add VGIC data structures for the nesting Jintack Lim
2017-01-09  6:24 ` [RFC 27/55] KVM: arm/arm64: Emulate GICH interface on GICv2 Jintack Lim
2017-02-22 13:06   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 28/55] KVM: arm/arm64: Prepare vgic state for the nested VM Jintack Lim
2017-02-22 13:12   ` Christoffer Dall [this message]
2017-01-09  6:24 ` [RFC 29/55] KVM: arm/arm64: Set up the prepared vgic state Jintack Lim
2017-01-09  6:24 ` [RFC 30/55] KVM: arm/arm64: Inject irqs to the guest hypervisor Jintack Lim
2017-02-22 13:16   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 31/55] KVM: arm/arm64: Inject maintenance interrupts " Jintack Lim
2017-02-22 13:19   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 32/55] KVM: arm/arm64: register GICH iodev for " Jintack Lim
2017-02-22 13:21   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 33/55] KVM: arm/arm64: Remove unused params in mmu functions Jintack Lim
2017-01-09  6:24 ` [RFC 34/55] KVM: arm/arm64: Abstract stage-2 MMU state into a separate structure Jintack Lim
2017-01-09  6:24 ` [RFC 35/55] KVM: arm/arm64: Support mmu for the virtual EL2 execution Jintack Lim
2017-02-22 13:38   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 36/55] KVM: arm64: Invalidate virtual EL2 TLB entries when needed Jintack Lim
2017-01-09  6:24 ` [RFC 37/55] KVM: arm64: Setup vttbr_el2 on each VM entry Jintack Lim
2017-01-09  6:24 ` [RFC 38/55] KVM: arm/arm64: Make mmu functions non-static Jintack Lim
2017-01-09  6:24 ` [RFC 39/55] KVM: arm/arm64: Add mmu context for the nesting Jintack Lim
2017-02-22 13:34   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 40/55] KVM: arm/arm64: Handle vttbr_el2 write operation from the guest hypervisor Jintack Lim
2017-02-22 17:59   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 41/55] KVM: arm/arm64: Unmap/flush shadow stage 2 page tables Jintack Lim
2017-02-22 18:09   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 42/55] KVM: arm64: Implement nested Stage-2 page table walk logic Jintack Lim
2017-01-09  6:24 ` [RFC 43/55] KVM: arm/arm64: Handle shadow stage 2 page faults Jintack Lim
2017-01-09  6:24 ` [RFC 44/55] KVM: arm/arm64: Move kvm_is_write_fault to header file Jintack Lim
2017-01-09  6:24 ` [RFC 45/55] KVM: arm64: KVM: Inject stage-2 page faults Jintack Lim
2017-01-09  6:24 ` [RFC 46/55] KVM: arm64: Add more info to the S2 translation result Jintack Lim
2017-01-09  6:24 ` [RFC 47/55] KVM: arm/arm64: Forward the guest hypervisor's stage 2 permission faults Jintack Lim
2017-02-22 18:15   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 48/55] KVM: arm64: Emulate TLBI instruction Jintack Lim
2017-01-09  6:24 ` [RFC 49/55] KVM: arm64: Fixes to toggle_cache for nesting Jintack Lim
2017-01-09  6:24 ` [RFC 50/55] KVM: arm/arm64: Abstract kvm_phys_addr_ioremap() function Jintack Lim
2017-01-09  6:24 ` [RFC 51/55] KVM: arm64: Expose physical address of vcpu interface Jintack Lim
2017-01-09  6:24 ` [RFC 52/55] KVM: arm/arm64: Create a vcpu mapping for the nested VM Jintack Lim
2017-01-09  6:24 ` [RFC 53/55] KVM: arm64: Reflect shadow VMPIDR_EL2 value to MPIDR_EL1 Jintack Lim
2017-01-09  6:24 ` [RFC 54/55] KVM: arm/arm64: Adjust virtual offset considering nesting Jintack Lim
2017-02-22 19:28   ` Christoffer Dall
2017-01-09  6:24 ` [RFC 55/55] KVM: arm64: Enable nested virtualization Jintack Lim
2017-01-09 15:05 ` [RFC 00/55] Nested Virtualization on KVM/ARM David Hildenbrand
2017-01-10 16:18   ` Jintack Lim
2017-02-22 18:23 ` Christoffer Dall
2017-02-24 10:28   ` Jintack Lim

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