From: plaes@plaes.org (Priit Laes)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: sunxi-ng: sun5i: Fix mux width for csi clock
Date: Thu, 2 Mar 2017 22:55:27 +0200 [thread overview]
Message-ID: <20170302205527.23007-1-plaes@plaes.org> (raw)
Mux for CSI clock is 3 bits, not 2.
Signed-off-by: Priit Laes <plaes@plaes.org>
---
drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index 06edaa5..5c476f9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
csi_parents, csi_table,
- 0x134, 0, 5, 24, 2, BIT(31), 0);
+ 0x134, 0, 5, 24, 3, BIT(31), 0);
static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve",
0x13c, BIT(31), CLK_SET_RATE_PARENT);
--
2.9.3
next reply other threads:[~2017-03-02 20:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-02 20:55 Priit Laes [this message]
2017-03-03 7:12 ` [PATCH] clk: sunxi-ng: sun5i: Fix mux width for csi clock Maxime Ripard
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