From: andre.przywara@arm.com (Andre Przywara)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] irqchip/gic-v3-its: always check for cacheability attributes
Date: Thu, 16 Mar 2017 17:05:42 +0000 [thread overview]
Message-ID: <20170316170542.3568-3-andre.przywara@arm.com> (raw)
In-Reply-To: <20170316170542.3568-1-andre.przywara@arm.com>
Currently we only enable cache flushing if the redistributor denied
our shareability attribute, because we turn off cacheability in this
case.
But if it would just turn down our cacheability request, we would miss
setting the flag.
Re-check the cacheability attribute as reported back by the
redistributor to make sure we flush properly if needed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index b777c57..5cd4d58 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1156,7 +1156,12 @@ static int its_cpu_init_lpis(void)
GICR_PROPBASER_CACHEABILITY_MASK);
val |= GICR_PROPBASER_nC;
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
}
+ }
+
+ if (((tmp & GICR_PROPBASER_CACHEABILITY_MASK) == GICR_PROPBASER_nC) ||
+ ((tmp & GICR_PROPBASER_CACHEABILITY_MASK) == GICR_PROPBASER_nCnB)) {
pr_info_once("GIC: using cache flushing for LPI property table\n");
gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
}
--
2.9.0
prev parent reply other threads:[~2017-03-16 17:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-16 17:05 [PATCH 0/2] irqchip/gic-v3-its: LPI tables fixes Andre Przywara
2017-03-16 17:05 ` [PATCH 1/2] irqchip/gic-v3-its: bail out on already enabled LPIs Andre Przywara
2017-03-16 17:25 ` Shanker Donthineni
2017-03-17 9:46 ` Marc Zyngier
2017-03-17 10:43 ` Shanker Donthineni
2017-03-17 11:01 ` Marc Zyngier
2017-03-16 17:05 ` Andre Przywara [this message]
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