[PATCH v2 0/4] RK3399 dw-mipi-dsi patches

[PATCH v2 0/4] RK3399 dw-mipi-dsi patches

[Chris Zhong]

Hi all

This series set the phy_cfg_clk to be a required clock for RK3399, and
add a grf clock control in dw-mipi-dsi driver. And then correct a
register name.


Changes in v2:
- check the grf_clk only for RK3399

Chris Zhong (4):
  drm/rockchip/dsi: check phy_cfg_clk only for RK3399
  dt-bindings: add the grf clock for dw-mipi-dsi
  drm/rockchip/dsi: enable the grf clk before writing grf registers
  drm/rockchip/dsi: correct the grf_switch_reg name

 .../display/rockchip/dw_mipi_dsi_rockchip.txt      |  2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c             | 35 +++++++++++++++++-----
 2 files changed, 28 insertions(+), 9 deletions(-)

-- 
2.6.3

[PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

[Chris Zhong]

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

Changes in v2: None

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index f84f9ae..11c4166 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -1227,15 +1227,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 		clk_disable_unprepare(dsi->pclk);
 	}
 
-	dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
-	if (IS_ERR(dsi->phy_cfg_clk)) {
-		ret = PTR_ERR(dsi->phy_cfg_clk);
-		if (ret != -ENOENT) {
+	if (pdata == &rk3399_mipi_dsi_drv_data) {
+		dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+		if (IS_ERR(dsi->phy_cfg_clk)) {
+			ret = PTR_ERR(dsi->phy_cfg_clk);
 			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
 			return ret;
 		}
-		dsi->phy_cfg_clk = NULL;
-		dev_dbg(dev, "have not phy_cfg_clk\n");
 	}
 
 	ret = clk_prepare_enable(dsi->pllref_clk);
-- 
2.6.3

[PATCH v2 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

[Chris Zhong]

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

Changes in v2: None

 .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 188f6f7..7e17a60 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -10,7 +10,7 @@ Required properties:
 - interrupts: Represent the controller's interrupt to the CPU(s).
 - clocks, clock-names: Phandles to the controller's pll reference
   clock(ref) and APB clock(pclk). For RK3399, a phy config clock
-  (phy_cfg) is additional required. As described in [1].
+  (phy_cfg) and a grf clock(grf) are additional required. As described in [1].
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
-- 
2.6.3

[PATCH v2 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

[Chris Zhong]

For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

Changes in v2:
- check the grf_clk only for RK3399

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 11c4166..a4c74c7 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -291,6 +291,7 @@ struct dw_mipi_dsi {
 	struct regmap *grf_regmap;
 	void __iomem *base;
 
+	struct clk *grf_clk;
 	struct clk *pllref_clk;
 	struct clk *pclk;
 	struct clk *phy_cfg_clk;
@@ -979,6 +980,17 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	dw_mipi_dsi_dphy_interface_config(dsi);
 	dw_mipi_dsi_clear_err(dsi);
 
+	/*
+	 * For the RK3399, the clk of grf must be enabled before writing grf
+	 * register. And for RK3288 or other soc, this grf_clk must be NULL,
+	 * the clk_prepare_enable return true directly.
+	 */
+	ret = clk_prepare_enable(dsi->grf_clk);
+	if (ret) {
+		dev_err(dsi->dev, "Failed to enable grf_clk\n");
+		return;
+	}
+
 	if (pdata->grf_dsi0_mode_reg)
 		regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 			     pdata->grf_dsi0_mode);
@@ -1003,6 +1015,8 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 	dsi->dpms_mode = DRM_MODE_DPMS_ON;
+
+	clk_disable_unprepare(dsi->grf_clk);
 }
 
 static int
@@ -1234,6 +1248,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
 			return ret;
 		}
+
+		dsi->grf_clk = devm_clk_get(dev, "grf");
+		if (IS_ERR(dsi->grf_clk)) {
+			ret = PTR_ERR(dsi->grf_clk);
+			dev_err(dev, "Unable to get grf_clk: %d\n", ret);
+			return ret;
+		}
 	}
 
 	ret = clk_prepare_enable(dsi->pllref_clk);
-- 
2.6.3

[PATCH v2 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

[Chris Zhong]

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

Changes in v2: None

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index a4c74c7..20ad54d 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -34,7 +34,7 @@
 #define RK3288_DSI0_SEL_VOP_LIT		BIT(6)
 #define RK3288_DSI1_SEL_VOP_LIT		BIT(9)
 
-#define RK3399_GRF_SOC_CON19		0x6250
+#define RK3399_GRF_SOC_CON20		0x6250
 #define RK3399_DSI0_SEL_VOP_LIT		BIT(0)
 #define RK3399_DSI1_SEL_VOP_LIT		BIT(4)
 
@@ -1147,7 +1147,7 @@ static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
 	.dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
 	.dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
-	.grf_switch_reg = RK3399_GRF_SOC_CON19,
+	.grf_switch_reg = RK3399_GRF_SOC_CON20,
 	.grf_dsi0_mode = RK3399_GRF_DSI_MODE,
 	.grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
 	.max_data_lanes = 4,
-- 
2.6.3

[PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

[John Keeping]

On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote:

> For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
> disabled, MIPI phy can not work. Let's return a error if there is no
> phy_cfg_clk in dts property, when the pdata match RK3399.
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index f84f9ae..11c4166 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -1227,15 +1227,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
>  		clk_disable_unprepare(dsi->pclk);
>  	}
>  
> -	dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
> -	if (IS_ERR(dsi->phy_cfg_clk)) {
> -		ret = PTR_ERR(dsi->phy_cfg_clk);
> -		if (ret != -ENOENT) {
> +	if (pdata == &rk3399_mipi_dsi_drv_data) {

This will get messy if the next SOC also needs phy_cfg_clk.  Can we do
something like:

	if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
		...

> +		dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
> +		if (IS_ERR(dsi->phy_cfg_clk)) {
> +			ret = PTR_ERR(dsi->phy_cfg_clk);
>  			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
>  			return ret;
>  		}
> -		dsi->phy_cfg_clk = NULL;
> -		dev_dbg(dev, "have not phy_cfg_clk\n");
>  	}
>  
>  	ret = clk_prepare_enable(dsi->pllref_clk);

[PATCH v2 0/4] RK3399 dw-mipi-dsi patches

[Brian Norris]

On Thu, Mar 16, 2017 at 11:31:43AM +0800, Chris Zhong wrote:
> Hi all
> 
> This series set the phy_cfg_clk to be a required clock for RK3399, and
> add a grf clock control in dw-mipi-dsi driver. And then correct a
> register name.
> 
> 
> Changes in v2:
> - check the grf_clk only for RK3399

For the series:

Tested-by: Brian Norris <briannorris@chromium.org>

[PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

[Chris Zhong]

Hi John

On 03/16/2017 06:55 PM, John Keeping wrote:
> On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote:
>
>> For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
>> disabled, MIPI phy can not work. Let's return a error if there is no
>> phy_cfg_clk in dts property, when the pdata match RK3399.
>>
>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>> ---
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++------
>>   1 file changed, 4 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>> index f84f9ae..11c4166 100644
>> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>> @@ -1227,15 +1227,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
>>   		clk_disable_unprepare(dsi->pclk);
>>   	}
>>   
>> -	dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
>> -	if (IS_ERR(dsi->phy_cfg_clk)) {
>> -		ret = PTR_ERR(dsi->phy_cfg_clk);
>> -		if (ret != -ENOENT) {
>> +	if (pdata == &rk3399_mipi_dsi_drv_data) {
> This will get messy if the next SOC also needs phy_cfg_clk.  Can we do
> something like:
>
> 	if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
> 		...
Thanks, good idea. I think RK3368 mipi-dsi driver is on the way. :)


>> +		dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
>> +		if (IS_ERR(dsi->phy_cfg_clk)) {
>> +			ret = PTR_ERR(dsi->phy_cfg_clk);
>>   			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
>>   			return ret;
>>   		}
>> -		dsi->phy_cfg_clk = NULL;
>> -		dev_dbg(dev, "have not phy_cfg_clk\n");
>>   	}
>>   
>>   	ret = clk_prepare_enable(dsi->pllref_clk);
>
>

-- 
Chris Zhong