From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 10/17] arm64: Add CNTVCT_EL0 trap handler
Date: Mon, 20 Mar 2017 14:52:07 +0000 [thread overview]
Message-ID: <20170320145204.GG31213@leverpostej> (raw)
In-Reply-To: <20170306112622.13853-11-marc.zyngier@arm.com>
On Mon, Mar 06, 2017 at 11:26:15AM +0000, Marc Zyngier wrote:
> Since people seem to make a point in breaking the userspace visible
> counter, we have no choice but to trap the access. Add the required
> handler.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm64/include/asm/esr.h | 2 ++
> arch/arm64/kernel/traps.c | 14 ++++++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index d14c478976d0..ad42e79a5d4d 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -175,6 +175,8 @@
> #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
> ESR_ELx_SYS64_ISS_DIR_READ)
>
> +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
> + ESR_ELx_SYS64_ISS_DIR_READ)
> #ifndef __ASSEMBLY__
> #include <asm/types.h>
>
> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> index e52be6aa44ee..1de444e6c669 100644
> --- a/arch/arm64/kernel/traps.c
> +++ b/arch/arm64/kernel/traps.c
> @@ -505,6 +505,14 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
> regs->pc += 4;
> }
>
> +static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
> +{
> + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
> +
> + pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
> + regs->pc += 4;
> +}
I was going to suggest it'd be worth using AARCH64_INSN_SIZE, but I see
most of the other handlers in this file don't, so I guess that's not a
big deal.
Otherwise, this looks fine to me. FWIW:
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> struct sys64_hook {
> unsigned int esr_mask;
> unsigned int esr_val;
> @@ -523,6 +531,12 @@ static struct sys64_hook sys64_hooks[] = {
> .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
> .handler = ctr_read_handler,
> },
> + {
> + /* Trap read access to CNTVCT_EL0 */
> + .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
> + .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
> + .handler = cntvct_read_handler,
> + },
> {},
> };
>
> --
> 2.11.0
>
next prev parent reply other threads:[~2017-03-20 14:52 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-06 11:26 [PATCH 00/17] clocksource/arch_timer: Errara workaround infrastructure rework Marc Zyngier
2017-03-06 11:26 ` [PATCH 01/17] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier
2017-03-07 13:03 ` Hanjun Guo
2017-03-20 13:51 ` Mark Rutland
2017-03-06 11:26 ` [PATCH 02/17] arm64: arch_timer: Add erratum handler for globally defined capability Marc Zyngier
2017-03-06 11:26 ` [PATCH 03/17] arm64: Allow checking of a CPU-local erratum Marc Zyngier
2017-03-20 13:56 ` Mark Rutland
2017-03-20 14:09 ` Suzuki K Poulose
2017-03-06 11:26 ` [PATCH 04/17] arm64: arch_timer: Add erratum handler for CPU-specific capability Marc Zyngier
2017-03-06 11:26 ` [PATCH 05/17] arm64: arch_timer: Move arch_timer_reg_read/write around Marc Zyngier
2017-03-20 13:59 ` Mark Rutland
2017-03-06 11:26 ` [PATCH 06/17] arm64: arch_timer: Get rid of erratum_workaround_set_sne Marc Zyngier
2017-03-20 14:06 ` Mark Rutland
2017-03-20 16:59 ` Marc Zyngier
2017-03-06 11:26 ` [PATCH 07/17] arm64: arch_timer: Rework the set_next_event workarounds Marc Zyngier
2017-03-07 13:25 ` Hanjun Guo
2017-03-06 11:26 ` [PATCH 08/17] arm64: arch_timer: Make workaround methods optional Marc Zyngier
2017-03-06 11:26 ` [PATCH 09/17] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Marc Zyngier
2017-03-06 11:26 ` [PATCH 10/17] arm64: Add CNTVCT_EL0 trap handler Marc Zyngier
2017-03-20 14:52 ` Mark Rutland [this message]
2017-03-06 11:26 ` [PATCH 11/17] arm64: arch_timer: Move clocksource_counter and co around Marc Zyngier
2017-03-06 11:26 ` [PATCH 12/17] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier
2017-03-06 11:26 ` [PATCH 13/17] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Marc Zyngier
2017-03-20 14:56 ` Mark Rutland
2017-03-20 15:30 ` Suzuki K Poulose
2017-03-06 11:26 ` [PATCH 14/17] arm64: Define Cortex-A73 MIDR Marc Zyngier
2017-03-06 11:26 ` [PATCH 15/17] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Marc Zyngier
2017-03-20 14:58 ` Mark Rutland
2017-03-06 11:26 ` [PATCH 16/17] arm64: arch_timer: Allow erratum matching with ACPI OEM information Marc Zyngier
2017-03-07 13:12 ` Hanjun Guo
2017-03-06 11:26 ` [PATCH 17/17] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Marc Zyngier
2017-03-07 13:19 ` Hanjun Guo
2017-03-20 15:00 ` Mark Rutland
2017-03-06 21:48 ` [PATCH 00/17] clocksource/arch_timer: Errara workaround infrastructure rework dann frazier
2017-03-07 12:56 ` Hanjun Guo
2017-03-20 15:07 ` Mark Rutland
2017-03-20 15:25 ` Marc Zyngier
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