* [PATCH 01/32] arm64: dts: r8a7796: Add I2C for DVFS device node
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 02/32] arm64: dts: r8a7796: salvator-x: Add I2C for DVFS device support Simon Horman
` (31 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Dien Pham <dien.pham.ry@rvc.renesas.com>
This patch adds I2C for DVFS device node for R8A7796 SoC.
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f7120cdedd0d..c95ad177b097 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -25,6 +25,7 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ i2c7 = &i2c_dvfs;
};
psci {
@@ -269,6 +270,19 @@
#power-domain-cells = <1>;
};
+ i2c_dvfs: i2c at e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7796",
+ "renesas,rcar-gen3-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
i2c0: i2c at e6500000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 02/32] arm64: dts: r8a7796: salvator-x: Add I2C for DVFS device support
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
2017-03-20 8:57 ` [PATCH 01/32] arm64: dts: r8a7796: Add I2C for DVFS device node Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 03/32] arm64: dts: r8a7795: Add I2C for DVFS core to dtsi Simon Horman
` (30 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Dien Pham <dien.pham.ry@rvc.renesas.com>
This patch adds support of I2C for DVFS device for Salvator-X board on
R8A7796 SoC.
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index c7f40f8f3169..61f4662db497 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -261,3 +261,7 @@
timeout-sec = <60>;
status = "okay";
};
+
+&i2c_dvfs {
+ status = "okay";
+};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 03/32] arm64: dts: r8a7795: Add I2C for DVFS core to dtsi
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
2017-03-20 8:57 ` [PATCH 01/32] arm64: dts: r8a7796: Add I2C for DVFS device node Simon Horman
2017-03-20 8:57 ` [PATCH 02/32] arm64: dts: r8a7796: salvator-x: Add I2C for DVFS device support Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 04/32] arm64: dts: r8a7795: salvator-x: Enable I2C for DVFS device Simon Horman
` (29 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
This patch adds I2C for DVFS device support for R8A7795 SoC.
Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index eac4f29aa5cd..fe266bb3d913 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -25,6 +25,7 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ i2c7 = &i2c_dvfs;
};
psci {
@@ -793,6 +794,19 @@
status = "disabled";
};
+ i2c_dvfs: i2c at e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7795",
+ "renesas,rcar-gen3-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
i2c0: i2c at e6500000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 04/32] arm64: dts: r8a7795: salvator-x: Enable I2C for DVFS device
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (2 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 03/32] arm64: dts: r8a7795: Add I2C for DVFS core to dtsi Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 05/32] arm64: dts: h3ulcb: Update memory node to 4 GiB map Simon Horman
` (28 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
This patch enables I2C for DVFS device for for Salvator-X board on
R8A7795 SoC.
Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 7a8986edcdc0..dc1177c76aa5 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -485,6 +485,10 @@
clock-frequency = <22579200>;
};
+&i2c_dvfs {
+ status = "okay";
+};
+
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 05/32] arm64: dts: h3ulcb: Update memory node to 4 GiB map
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (3 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 04/32] arm64: dts: r8a7795: salvator-x: Enable I2C for DVFS device Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 06/32] arm64: dts: r8a7795: Use rgmii-txid phy-mode for EthernetAVB Simon Horman
` (27 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
This patch adds memory region:
- After changes, the H3ULCB board has the following map:
Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff
Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff
- Before changes, the old map looked like this:
Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index c5f8f69a4f5f..9811534f296e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -33,6 +33,21 @@
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+ memory at 500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x40000000>;
+ };
+
+ memory at 600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
+ };
+
+ memory at 700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x40000000>;
+ };
+
leds {
compatible = "gpio-leds";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 06/32] arm64: dts: r8a7795: Use rgmii-txid phy-mode for EthernetAVB
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (4 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 05/32] arm64: dts: h3ulcb: Update memory node to 4 GiB map Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 07/32] arm64: dts: r8a7795: salvator-x: Fix EthernetAVB PHY timing Simon Horman
` (26 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Since commit 61fccb2d6274 ("ravb: Add tx and rx clock internal delays mode
of APSR") the EthernetAVB driver enables tx and rx clock internal delay
modes (TDM and RDM) depending on the phy mode as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
And prior to the above commit no internal delay mode settings were
implemented for any phy mode.
With this and the above change present tx internal delay mode is enabled
which has been observed to address failures in the case of 1Gbps
communication using the by salvator-x board with the KSZ9031RNX phy. This
has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W)
SoCs.
With the above patch present but this patch present tx and rx internal
delay modes are enabled; and with the above patch and this present absent
no internal delay modes are enabled. In both cases failures have been
observed when using 1Gbps communication in the environments described
above.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index fe266bb3d913..382a8987bca9 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -564,7 +564,7 @@
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 07/32] arm64: dts: r8a7795: salvator-x: Fix EthernetAVB PHY timing
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (5 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 06/32] arm64: dts: r8a7795: Use rgmii-txid phy-mode for EthernetAVB Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 08/32] arm64: dts: h3ulcb: " Simon Horman
` (25 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Set PHY rxc-skew-ps to 1500 and all other values to their default values.
This is intended to to address failures in the case of 1Gbps communication
using the by salvator-x board with the KSZ9031RNX phy. This has been
reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index dc1177c76aa5..5158ba3f9ce3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -497,18 +497,7 @@
status = "okay";
phy0: ethernet-phy at 0 {
- rxc-skew-ps = <900>;
- rxdv-skew-ps = <0>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txc-skew-ps = <900>;
- txen-skew-ps = <0>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
+ rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 08/32] arm64: dts: h3ulcb: Fix EthernetAVB PHY timing
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (6 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 07/32] arm64: dts: r8a7795: salvator-x: Fix EthernetAVB PHY timing Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 09/32] arm64: dts: r8a7796: Use rgmii-txid phy-mode for EthernetAVB Simon Horman
` (24 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Set PHY rxc-skew-ps to 1500 and all other values to their default values.
This is intended to to address failures in the case of 1Gbps communication
using the by h3ulcb board with the KSZ9031RNX phy.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 9811534f296e..69c623faf80c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -354,18 +354,7 @@
status = "okay";
phy0: ethernet-phy at 0 {
- rxc-skew-ps = <900>;
- rxdv-skew-ps = <0>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txc-skew-ps = <900>;
- txen-skew-ps = <0>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
+ rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 09/32] arm64: dts: r8a7796: Use rgmii-txid phy-mode for EthernetAVB
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (7 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 08/32] arm64: dts: h3ulcb: " Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 10/32] arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing Simon Horman
` (23 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Since commit 61fccb2d6274 ("ravb: Add tx and rx clock internal delays mode
of APSR") the EthernetAVB driver enables tx and rx clock internal delay
modes (TDM and RDM) depending on the phy mode as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
And prior to the above commit no internal delay mode settings were
implemented for any phy mode.
With this and the above change present tx internal delay mode is enabled
which has been observed to address failures in the case of 1Gbps
communication using the by salvator-x board with the KSZ9031RNX phy. This
has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W)
SoCs.
With the above patch present but this patch present tx and rx internal
delay modes are enabled; and with the above patch and this present absent
no internal delay modes are enabled. In both cases failures have been
observed when using 1Gbps communication in the environments described
above.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c95ad177b097..1c1c1eae9cba 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -483,7 +483,7 @@
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 10/32] arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (8 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 09/32] arm64: dts: r8a7796: Use rgmii-txid phy-mode for EthernetAVB Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 11/32] arm64: dts: r8a7796 dtsi: Add all HSCIF nodes Simon Horman
` (22 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Set PHY rxc-skew-ps to 1500 and all other values to their default values.
This is intended to to address failures in the case of 1Gbps communication
using the by salvator-x board with the KSZ9031RNX phy. This has been
reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 61f4662db497..93ed23ab71bb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -172,18 +172,7 @@
status = "okay";
phy0: ethernet-phy at 0 {
- rxc-skew-ps = <900>;
- rxdv-skew-ps = <0>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txc-skew-ps = <900>;
- txen-skew-ps = <0>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
+ rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 11/32] arm64: dts: r8a7796 dtsi: Add all HSCIF nodes
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (9 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 10/32] arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 12/32] arm64: dts: r8a7796: Add all SCIF nodes Simon Horman
` (21 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Add the device nodes for all HSCIF serial ports, incl. clocks, and
power domain.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: express register size in hex; refer to power domain in changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 1c1c1eae9cba..714fd96b29eb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -489,6 +489,76 @@
status = "disabled";
};
+ hscif0: serial at e6540000 {
+ compatible = "renesas,hscif-r8a7796",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial at e6550000 {
+ compatible = "renesas,hscif-r8a7796",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial at e6560000 {
+ compatible = "renesas,hscif-r8a7796",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif3: serial at e66a0000 {
+ compatible = "renesas,hscif-r8a7796",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif4: serial at e66b0000 {
+ compatible = "renesas,hscif-r8a7796",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
scif2: serial at e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 12/32] arm64: dts: r8a7796: Add all SCIF nodes
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (10 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 11/32] arm64: dts: r8a7796 dtsi: Add all HSCIF nodes Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 13/32] arm64: dts: r8a7796: Enable SCIF DMA Simon Horman
` (20 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks
and power domain.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 65 ++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 714fd96b29eb..5fb93fc043c2 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -559,6 +559,32 @@
status = "disabled";
};
+ scif0: serial at e6e60000 {
+ compatible = "renesas,scif-r8a7796",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial at e6e68000 {
+ compatible = "renesas,scif-r8a7796",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
scif2: serial at e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
@@ -572,6 +598,45 @@
status = "disabled";
};
+ scif3: serial at e6c50000 {
+ compatible = "renesas,scif-r8a7796",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial at e6c40000 {
+ compatible = "renesas,scif-r8a7796",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial at e6f30000 {
+ compatible = "renesas,scif-r8a7796",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 64>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
msiof0: spi at e6e90000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 13/32] arm64: dts: r8a7796: Enable SCIF DMA
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (11 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 12/32] arm64: dts: r8a7796: Add all SCIF nodes Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 14/32] arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1) Simon Horman
` (19 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 5fb93fc043c2..951e351ddae1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -568,6 +568,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -581,6 +584,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -607,6 +613,8 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -620,6 +628,8 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -633,6 +643,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 14/32] arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1)
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (12 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 13/32] arm64: dts: r8a7796: Enable SCIF DMA Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 15/32] arm64: dts: r8a7796: Enable HSCIF DMA Simon Horman
` (18 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Enables the SCIF hooked up to the DEBUG1 connector.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 93ed23ab71bb..74b8c653c9fe 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -18,6 +18,7 @@
aliases {
serial0 = &scif2;
+ serial1 = &scif1;
ethernet0 = &avb;
};
@@ -113,6 +114,11 @@
function = "avb";
};
+ scif1_pins: scif1 {
+ groups = "scif1_data_a", "scif1_ctrl";
+ function = "scif1";
+ };
+
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
@@ -228,6 +234,14 @@
status = "okay";
};
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 15/32] arm64: dts: r8a7796: Enable HSCIF DMA
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (13 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 14/32] arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1) Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 16/32] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Simon Horman
` (17 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 951e351ddae1..aa404ed9142e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -499,6 +499,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -513,6 +516,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -527,6 +533,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -541,6 +550,8 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
@@ -555,6 +566,8 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 16/32] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (14 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 15/32] arm64: dts: r8a7796: Enable HSCIF DMA Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 17/32] arm64: dts: r8a7795: Add Cortex-A53 PMU node Simon Horman
` (16 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).
Based on work by Takeshi Kihara and Dirk Behme.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 ++++++++++++++++++++++++++++----
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 382a8987bca9..61830697e33c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -73,6 +73,42 @@
enable-method = "psci";
};
+ a53_0: cpu at 100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_1: cpu at 101 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu at 102 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu at 103 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA57: cache-controller at 0 {
compatible = "cache";
reg = <0>;
@@ -166,7 +202,7 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -307,13 +343,13 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller at e6150000 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 17/32] arm64: dts: r8a7795: Add Cortex-A53 PMU node
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (15 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 16/32] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 18/32] arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM Simon Horman
` (15 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Enable the performance monitor unit for the Cortex-A53 cores on the
R8A7795 SoC.
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 61830697e33c..3573872974e0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -340,6 +340,18 @@
<&a57_3>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 18/32] arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (16 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 17/32] arm64: dts: r8a7795: Add Cortex-A53 PMU node Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 19/32] arm64: dts: r8a7796: " Simon Horman
` (14 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
>From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI
function call. Hence, upgrade PSCI version for R-Car H3 to support
Suspend-to-RAM.
The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support
since necessary callback functions will be registered after a query
to ARM Trusted Firmware about SYSTEM_SUSPEND support.
Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and
CPUIdle should be able to work normally with this change.
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Keep "arm,psci-0.2"]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 3573872974e0..c1e00a3e7c45 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -29,7 +29,7 @@
};
psci {
- compatible = "arm,psci-0.2";
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 19/32] arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (17 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 18/32] arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 20/32] arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches Simon Horman
` (13 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
>From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI
function call. Hence, upgrade PSCI version for R-Car M3-W to support
Suspend-to-RAM.
The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support
since necessary callback functions will be registered after a query
to ARM Trusted Firmware about SYSTEM_SUSPEND support.
Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and
CPUIdle should be able to work normally with this change.
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Keep "arm,psci-0.2"]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index aa404ed9142e..dbf82bc6ba64 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -29,7 +29,7 @@
};
psci {
- compatible = "arm,psci-0.2";
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 20/32] arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (18 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 19/32] arm64: dts: r8a7796: " Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 21/32] arm64: dts: r8a7796: Remove unit-address and reg from integrated cache Simon Horman
` (12 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
The Cortex-A57/A53 cache controllers are integrated controllers, and
thus the device nodes representing them should not have unit-addresses
or reg properties.
Fixes: 6f7bf82cc912441f ("arm64: dts: r8a7795: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index c1e00a3e7c45..14772bc02125 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -109,17 +109,15 @@
enable-method = "psci";
};
- L2_CA57: cache-controller at 0 {
+ L2_CA57: cache-controller-0 {
compatible = "cache";
- reg = <0>;
power-domains = <&sysc R8A7795_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
- L2_CA53: cache-controller at 100 {
+ L2_CA53: cache-controller-1 {
compatible = "cache";
- reg = <0x100>;
power-domains = <&sysc R8A7795_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 21/32] arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (19 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 20/32] arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 22/32] arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins Simon Horman
` (11 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
The Cortex-A57 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 1561f20760ec96db ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index dbf82bc6ba64..27f7dd9bd988 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -47,9 +47,8 @@
enable-method = "psci";
};
- L2_CA57: cache-controller at 0 {
+ L2_CA57: cache-controller-0 {
compatible = "cache";
- reg = <0>;
power-domains = <&sysc R8A7796_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 22/32] arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (20 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 21/32] arm64: dts: r8a7796: Remove unit-address and reg from integrated cache Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 23/32] arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC Simon Horman
` (10 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
The EthernetAVB should not depend on the bootloader to setup correct
drive-strength values. Values for drive-strength where found by
examining the registers after the bootloader has configured the
registers and successfully used the EthernetAVB.
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 5158ba3f9ce3..277ab8484e0c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -247,8 +247,22 @@
};
avb_pins: avb {
- groups = "avb_mdc";
- function = "avb";
+ mux {
+ groups = "avb_link", "avb_phy_int", "avb_mdc",
+ "avb_mii";
+ function = "avb";
+ };
+
+ pins_mdc {
+ groups = "avb_mdc";
+ drive-strength = <24>;
+ };
+
+ pins_mii_tx {
+ pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+ "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+ drive-strength = <12>;
+ };
};
du_pins: du {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 23/32] arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (21 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 22/32] arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 24/32] arm64: dts: r8a7796: Add Cortex-A57 CPU cores Simon Horman
` (9 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1.
Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0.
Because of this, current platform board (using SRC/DVC/SSI)
Playback/Capture both will use same Audio-DMAC0
(but it depends on audio data path).
First note is that this "rx" and "tx" are from each IP point,
it doesn't mean Playback/Capture.
Second note is that Audio DMAC assigned on DT is only for
Audio-DMAC, Audio-DMAC-peri-peri has no entry.
=> Audio-DMAC
-> Audio-DMAC-peri-peri
-- HW connection
Playback case
[Mem] => [SRC]--[DVC] -> [SSI]--[Codec]
rx ~~~~~~~~~~~~
Capture
[Mem] <= [DVC]--[SRC] <- [SSI]--[Codec]
tx ~~~~~~~~~~~~
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 14772bc02125..55c09f1b89c9 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1075,11 +1075,11 @@
rcar_sound,dvc {
dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
+ dmas = <&audma1 0xbc>;
dma-names = "tx";
};
dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
+ dmas = <&audma1 0xbe>;
dma-names = "tx";
};
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 24/32] arm64: dts: r8a7796: Add Cortex-A57 CPU cores
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (22 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 23/32] arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 25/32] arm64: dts: r8a7796: Add Cortex-A57 PMU node Simon Horman
` (8 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds Cortex-A57 CPU cores to R8A7796 SoC for a total of
2 x Cortex-A57.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Rebased]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 27f7dd9bd988..d2a2110fc7fc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -37,7 +37,6 @@
#address-cells = <1>;
#size-cells = <0>;
- /* 1 core only at this point */
a57_0: cpu at 0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
@@ -47,6 +46,15 @@
enable-method = "psci";
};
+ a57_1: cpu at 1 {
+ compatible = "arm,cortex-a57","arm,armv8";
+ reg = <0x1>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
+ next-level-cache = <&L2_CA57>;
+ enable-method = "psci";
+ };
+
L2_CA57: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A7796_PD_CA57_SCU>;
@@ -100,7 +108,7 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -109,13 +117,13 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
wdt0: watchdog at e6020000 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 25/32] arm64: dts: r8a7796: Add Cortex-A57 PMU node
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (23 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 24/32] arm64: dts: r8a7796: Add Cortex-A57 CPU cores Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 26/32] arm64: dts: r8a7796: Add CA53 L2 cache-controller node Simon Horman
` (7 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Enable the performance monitor unit for the Cortex-A57 cores on the
R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index d2a2110fc7fc..454e1292f910 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -252,6 +252,14 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ pmu_a57 {
+ compatible = "arm,cortex-a57-pmu";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a57_0>,
+ <&a57_1>;
+ };
+
cpg: clock-controller at e6150000 {
compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 26/32] arm64: dts: r8a7796: Add CA53 L2 cache-controller node
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (24 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 25/32] arm64: dts: r8a7796: Add Cortex-A57 PMU node Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 27/32] arm64: dts: r8a7796: Add Cortex-A53 CPU cores Simon Horman
` (6 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 454e1292f910..b951f5ffe9e0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -61,6 +61,13 @@
cache-unified;
cache-level = <2>;
};
+
+ L2_CA53: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7796_PD_CA53_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
extal_clk: extal {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 27/32] arm64: dts: r8a7796: Add Cortex-A53 CPU cores
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (25 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 26/32] arm64: dts: r8a7796: Add CA53 L2 cache-controller node Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 28/32] arm64: dts: r8a7796: Add Cortex-A53 PMU node Simon Horman
` (5 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of
6 cores (2 x Cortex-A57 + 4 x Cortex-A53).
Based on a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 46 ++++++++++++++++++++++++++++----
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index b951f5ffe9e0..b32a180009dd 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -55,6 +55,42 @@
enable-method = "psci";
};
+ a53_0: cpu at 100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_1: cpu at 101 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu at 102 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu at 103 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA57: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A7796_PD_CA57_SCU>;
@@ -115,7 +151,7 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -124,13 +160,13 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
wdt0: watchdog at e6020000 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 28/32] arm64: dts: r8a7796: Add Cortex-A53 PMU node
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (26 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 27/32] arm64: dts: r8a7796: Add Cortex-A53 CPU cores Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 29/32] arm64: dts: h3ulcb: Drop superfluous status update for frequency override Simon Horman
` (4 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Enable the performance monitor unit for the Cortex-A53 cores on the
R8A7796 SoC.
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index b32a180009dd..a90abf14dc4e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -303,6 +303,18 @@
<&a57_1>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
+ };
+
cpg: clock-controller at e6150000 {
compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 29/32] arm64: dts: h3ulcb: Drop superfluous status update for frequency override
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (27 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 28/32] arm64: dts: r8a7796: Add Cortex-A53 PMU node Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 30/32] arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides Simon Horman
` (3 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
The scif_clk device node is already enabled in r8a7795.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 69c623faf80c..ab352159de65 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -228,7 +228,6 @@
&scif_clk {
clock-frequency = <14745600>;
- status = "okay";
};
&i2c2 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 30/32] arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (28 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 29/32] arm64: dts: h3ulcb: Drop superfluous status update for frequency override Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 31/32] arm64: dts: m3ulcb: Drop superfluous status update for frequency override Simon Horman
` (2 subsequent siblings)
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
The scif_clk and pcie_bus_clk device nodes are already enabled in
r8a7795.dtsi, so there is no need to update their statuses again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 277ab8484e0c..f25241921067 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -362,7 +362,6 @@
&scif_clk {
clock-frequency = <14745600>;
- status = "okay";
};
&i2c2 {
@@ -574,7 +573,6 @@
&pcie_bus_clk {
clock-frequency = <100000000>;
- status = "okay";
};
&pciec0 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 31/32] arm64: dts: m3ulcb: Drop superfluous status update for frequency override
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (29 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 30/32] arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-20 8:57 ` [PATCH 32/32] arm64: dts: r8a7796: salvator-x: " Simon Horman
2017-03-22 0:34 ` [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Olof Johansson
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
The scif_clk device node is already enabled in r8a7796.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index c3f064ac2cb4..372b2a944716 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -180,7 +180,6 @@
&scif_clk {
clock-frequency = <14745600>;
- status = "okay";
};
&wdt0 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 32/32] arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (30 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 31/32] arm64: dts: m3ulcb: Drop superfluous status update for frequency override Simon Horman
@ 2017-03-20 8:57 ` Simon Horman
2017-03-22 0:34 ` [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Olof Johansson
32 siblings, 0 replies; 34+ messages in thread
From: Simon Horman @ 2017-03-20 8:57 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
The scif_clk device node is already enabled in r8a7796.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 74b8c653c9fe..c9f59b6ce33f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -250,7 +250,6 @@
&scif_clk {
clock-frequency = <14745600>;
- status = "okay";
};
&i2c2 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 34+ messages in thread* [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12
2017-03-20 8:57 [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.12 Simon Horman
` (31 preceding siblings ...)
2017-03-20 8:57 ` [PATCH 32/32] arm64: dts: r8a7796: salvator-x: " Simon Horman
@ 2017-03-22 0:34 ` Olof Johansson
32 siblings, 0 replies; 34+ messages in thread
From: Olof Johansson @ 2017-03-22 0:34 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Mar 20, 2017 at 09:57:30AM +0100, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM64 based SoC DT updates for v4.12.
>
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt-for-v4.12
>
> for you to fetch changes up to 3cbe33367d4fd480a92fbc131a96fa925be9e95d:
>
> arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override (2017-03-13 10:21:16 +0100)
>
> ----------------------------------------------------------------
> Renesas ARM64 Based SoC DT Updates for v4.12
>
> Cleanup:
> * Drop superfluous status update for frequency override from all
> r8a779[56] boards
> * Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
> * Remove unit-address and reg from integrated cache on r8a779[56] SoCs
>
> Enhancements:
> * Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
> * Add Cortex-A53 CPU cores to r8a7795 SoC
> * Update memory node to 4 GiB map on h3ulcb board
> * Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
> * Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
> * Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
> * Set drive-strength for ravb pins for r8a7795/salvator-x board
> * Enable gigabit ethernet on r8a779[56]/salvator-x boards
> * Enable I2C for DVFS device r8a779[56]/salvator-x boards
Merged into next/dt64. Thanks!
-Olof
^ permalink raw reply [flat|nested] 34+ messages in thread