From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/2] clk: stm32f4: fix timeout management for pll and ready gate
Date: Wed, 5 Apr 2017 14:52:26 -0700 [thread overview]
Message-ID: <20170405215226.GG7065@codeaurora.org> (raw)
In-Reply-To: <1489652201-19889-3-git-send-email-gabriel.fernandez@st.com>
On 03/16, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> Use a classic polling to test bit ready.
> And the shift of the bit ready of LSE & LSI were wrongs.
>
> Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2017-04-05 21:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-16 8:16 [PATCH v2 0/2] STM32F4 clock fixes gabriel.fernandez at st.com
2017-03-16 8:16 ` [PATCH v2 1/2] clk: stm32f4: fix: exclude values 0 and 1 for PLLQ gabriel.fernandez at st.com
2017-04-05 21:52 ` Stephen Boyd
2017-03-16 8:16 ` [PATCH v2 2/2] clk: stm32f4: fix timeout management for pll and ready gate gabriel.fernandez at st.com
2017-04-05 21:52 ` Stephen Boyd [this message]
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