From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
Date: Thu, 27 Apr 2017 18:00:31 +0100 [thread overview]
Message-ID: <20170427170030.GF1890@arm.com> (raw)
In-Reply-To: <20170427164237.GA7114@leverpostej>
On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> > + /*
> > + * Override the size, for Cavium CN99xx implementations
> > + * which doesn't support the page 1 SMMU register space.
> > + */
> > + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> > + if (cpu_model == MIDR_THUNDERX_99XX ||
> > + cpu_model == MIDR_BRCM_VULCAN)
> > + size = SZ_64K;
>
> If you're trying to identify an SMMU erratum, identify the SMMU, not the
> CPU it happens to be paired with this time.
>
> There are ID registers in the SMMU you can use to do so.
>
> NAK to using the CPU ID here.
Agreed. I had some off-list discussion with Geetha where we agreed to use
the "silicon ID", which I assumed was the SMMU IIDR register.
Will
next prev parent reply other threads:[~2017-04-27 17:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-27 11:46 [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Geetha sowjanya
2017-04-27 11:46 ` [PATCH 1/3] arm64: Add MIDR values for Cavium cn99xx SoCs Geetha sowjanya
2017-04-27 13:01 ` Jayachandran C.
2017-04-27 11:46 ` [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha sowjanya
2017-04-27 16:42 ` Mark Rutland
2017-04-27 17:00 ` Will Deacon [this message]
2017-05-02 6:31 ` Geetha Akula
2017-05-03 9:47 ` Will Deacon
2017-05-03 10:32 ` Geetha Akula
2017-05-04 23:36 ` Jon Masters
2017-04-27 11:46 ` [PATCH 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 Geetha sowjanya
2017-04-27 13:39 ` [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Robert Richter
2017-04-27 16:37 ` Sunil Kovvuri
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