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From: ashok.raj@intel.com (Raj, Ashok)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING
Date: Tue, 2 May 2017 09:44:01 -0700	[thread overview]
Message-ID: <20170502164400.GA26406@linux.intel.com> (raw)
In-Reply-To: <758d0e431c732fe133e7b0e660bde5fc1beccdba.1493678834.git.leedom@chelsio.com>

Hi Casey


On Mon, May 01, 2017 at 04:13:50PM -0700, Casey Leedom wrote:
> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
> Ordering Attribute should not be used on Transaction Layer Packets destined
> for the PCIe End Node so flagged.  Initially flagged this way are Intel
> E5-26xx Root Complex Ports which suffer from a Flow Control Credit
> Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
> don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
> ---
>  drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++
>  include/linux/pci.h  |  2 ++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index f754453..4ae78b3 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -3979,6 +3979,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev)
>  			      quirk_tw686x_class);
>  
>  /*
> + * Some devices have problems with Transaction Layer Packets with the Relaxed
> + * Ordering Attribute set.  Such devices should mark themselves and other
> + * Device Drivers should check before sending TLPs with RO set.
> + */
> +static void quirk_relaxedordering_disable(struct pci_dev *dev)
> +{
> +	dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
> +}
> +
> +/*
> + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can
> + * cause performance problems with Upstream Transaction Layer Packets with
> + * Relaxed Ordering set.
> + */
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
> +			      quirk_relaxedordering_disable);
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
> +			      quirk_relaxedordering_disable);
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
> +			      quirk_relaxedordering_disable);
> +

You might want to add the RP ID's for both HSX/BDX. Tne entire range 
is 2F01H-2F0EH & 6F01H-6F0EH.

Cheers,
Ashok

  parent reply	other threads:[~2017-05-02 16:44 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-01 23:13 [PATCH 0/2] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Casey Leedom
2017-05-01 23:13 ` [PATCH 1/2] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Casey Leedom
2017-05-02  6:49   ` Ding Tianhong
2017-05-02 16:39   ` Alexander Duyck
2017-05-02 16:53     ` Raj, Ashok
2017-05-02 18:10       ` Alexander Duyck
2017-05-03  4:30         ` Casey Leedom
2017-05-03 16:02           ` Alexander Duyck
2017-05-04 21:01             ` Casey Leedom
2017-05-05 14:04               ` Alexander Duyck
2017-05-06  3:08                 ` Ding Tianhong
2017-05-06 18:07                   ` Alexander Duyck
2017-05-08 14:33                     ` Ding Tianhong
2017-05-08 15:22                       ` Alexander Duyck
2017-05-09  0:48                     ` Casey Leedom
2017-05-11  1:15                       ` Ding Tianhong
2017-05-16 18:38                         ` Casey Leedom
2017-05-17 14:49                           ` Alexander Duyck
2017-05-25 13:35                       ` Ding Tianhong
2017-05-25 19:49                         ` Alexander Duyck
2017-05-27 10:34                           ` Ding Tianhong
2017-05-02 16:44   ` Raj, Ashok [this message]
2017-05-01 23:13 ` [PATCH 2/2] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Casey Leedom
2017-05-02  0:56 ` [PATCH 0/2] Add " Ding Tianhong

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