From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
Date: Wed, 3 May 2017 10:47:18 +0100 [thread overview]
Message-ID: <20170503094717.GC8233@arm.com> (raw)
In-Reply-To: <CANHdaibvzp22XEa3NnKAKUtrHcWGc9oUcnM8KubcYCzEfOaKJg@mail.gmail.com>
Hi Geetha,
On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
Urgh, that's unfortunate. In what way is it broken?
> If using MIDR is not accepted, can we enable errata based on SMMU resource size?
> some thing like below.
No, you need to get your model number added to IORT after all if the IIDR
can't uniqely identify the part.
Sorry,
Will
next prev parent reply other threads:[~2017-05-03 9:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-27 11:46 [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Geetha sowjanya
2017-04-27 11:46 ` [PATCH 1/3] arm64: Add MIDR values for Cavium cn99xx SoCs Geetha sowjanya
2017-04-27 13:01 ` Jayachandran C.
2017-04-27 11:46 ` [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha sowjanya
2017-04-27 16:42 ` Mark Rutland
2017-04-27 17:00 ` Will Deacon
2017-05-02 6:31 ` Geetha Akula
2017-05-03 9:47 ` Will Deacon [this message]
2017-05-03 10:32 ` Geetha Akula
2017-05-04 23:36 ` Jon Masters
2017-04-27 11:46 ` [PATCH 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 Geetha sowjanya
2017-04-27 13:39 ` [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Robert Richter
2017-04-27 16:37 ` Sunil Kovvuri
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