From: robert.richter@cavium.com (Robert Richter)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds
Date: Sat, 6 May 2017 00:22:50 +0200 [thread overview]
Message-ID: <20170505222250.GY16981@rric.localdomain> (raw)
In-Reply-To: <1493986091-30521-1-git-send-email-gakula@caviumnetworks.com>
On 05.05.17 17:38:04, Geetha sowjanya wrote:
> From: Linu Cherian <linu.cherian@cavium.com>
>
> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
> SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
> SMMU doesnt support unique IRQ lines and also MSI for gerror,
> eventq and cmdq-sync
>
> The following patchset does software workaround for these two erratas.
>
> This series is based on patchset.
> https://www.spinics.net/lists/arm-kernel/msg578443.html
>
> Changes from v1:
> Since the use of MIDR register is rejected and SMMU_IIDR is broken on this
> silicon, as suggested by Will Deacon modified the patches to use ThunderX2
> SMMUv3 IORT model number to enable errata workaround.
>
> Changes from v2:
> Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document with
> new SMMU option used to enable errata workaround.
>
> Geetha Sowjanya (1):
> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
>
> Linu Cherian (6):
> iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for ThunderX2
> errata#74.
> iommu/arm-smmu-v3: Do resource size checks based on SMMU option
> PAGE0_REGS_ONLY
> ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition.
> iommu/arm-smmu-v3: For ACPI based device probing, set PAGE0_REGS_ONLY
> option for ThunderX2 SMMUv3 implementations.
> ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3
> model
> arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas
This split into patches does not look reasonable to me. 1 patch only
for each workaround should be sufficient.
-Robert
>
> Documentation/arm64/silicon-errata.txt | 2 +
> drivers/acpi/arm64/iort.c | 10 ++-
> drivers/iommu/arm-smmu-v3.c | 122 ++++++++++++++++++++++++++-------
> include/acpi/actbl2.h | 2 +
> 4 files changed, 110 insertions(+), 26 deletions(-)
>
> --
> 1.8.3.1
>
next prev parent reply other threads:[~2017-05-05 22:22 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-05 12:08 [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds Geetha sowjanya
2017-05-05 12:08 ` [PATCH v3 1/7] iommu/arm-smmu-v3: Introduce SMMU option PAGE0_REGS_ONLY for ThunderX2 errata #74 Geetha sowjanya
2017-05-05 22:26 ` Robert Richter
2017-05-05 23:03 ` Robert Richter
2017-05-08 9:17 ` Linu Cherian
2017-05-08 9:29 ` Robert Richter
2017-05-08 9:59 ` Robin Murphy
2017-05-08 10:04 ` Robert Richter
2017-05-05 12:08 ` [PATCH v3 2/7] iommu/arm-smmu-v3: Do resource size checks based on SMMU Geetha sowjanya
2017-05-05 22:18 ` Robert Richter
2017-05-08 9:44 ` Linu Cherian
2017-05-08 10:09 ` Robert Richter
2017-05-08 10:50 ` Linu Cherian
2017-05-08 12:21 ` Robert Richter
2017-05-08 11:03 ` Geetha Akula
2017-05-05 12:08 ` [PATCH v3 3/7] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition Geetha sowjanya
2017-05-05 13:53 ` Hanjun Guo
2017-05-05 14:56 ` David Daney
2017-05-05 14:58 ` Will Deacon
2017-05-05 15:33 ` Jon Masters
2017-05-05 12:08 ` [PATCH v3 4/7] iommu/arm-smmu-v3: For ACPI based device probing, set PAGE0_REGS_ONLY option for ThunderX2 SMMUv3 implementation Geetha sowjanya
2017-05-05 12:08 ` [PATCH v3 5/7] ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 model Geetha sowjanya
2017-05-05 22:19 ` Robert Richter
2017-05-05 12:08 ` [PATCH v3 6/7] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 Geetha sowjanya
2017-05-08 11:21 ` Robin Murphy
2017-05-08 12:02 ` Geetha Akula
2017-05-05 12:08 ` [PATCH v3 7/7] arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas Geetha sowjanya
2017-05-05 22:22 ` Robert Richter [this message]
2017-05-08 15:15 ` [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds Linu Cherian
2017-05-09 16:07 ` Robert Richter
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