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From: stillcompiling@gmail.com (Joshua Clayton)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v11 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed
Date: Thu, 25 May 2017 10:29:06 -0700	[thread overview]
Message-ID: <20170525172911.11467-2-stillcompiling@gmail.com> (raw)
In-Reply-To: <20170525172911.11467-1-stillcompiling@gmail.com>

From: Anatolij Gustschin <agust@denx.de>

Add a flag that is passed to the write_init() callback,
indicating that the SPI bitstream starts with LSB first.
SPI controllers usually send data with MSB first. If an
FPGA expects bitstream data as LSB first, the data must
be reversed either by the SPI controller or by the driver.

Alternatively the bitstream could be prepared as bit-reversed
to avoid the bit-swapping while sending. This flag indicates
such bit-reversed SPI bitstream. The low-level driver will
deal with the flag and perform bit-reversing if needed.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 include/linux/fpga/fpga-mgr.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index b4ac24c4411d..01c348ca38b7 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -67,10 +67,12 @@ enum fpga_mgr_states {
  * FPGA Manager flags
  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
  * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
+ * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
  */
 #define FPGA_MGR_PARTIAL_RECONFIG	BIT(0)
 #define FPGA_MGR_EXTERNAL_CONFIG	BIT(1)
 #define FPGA_MGR_ENCRYPTED_BITSTREAM	BIT(2)
+#define FPGA_MGR_BITSTREAM_LSB_FIRST	BIT(3)
 
 /**
  * struct fpga_image_info - information specific to a FPGA image
-- 
2.11.0

  reply	other threads:[~2017-05-25 17:29 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-25 17:29 [PATCH v11 0/6] FPGA Manager support for altera passive serial Joshua Clayton
2017-05-25 17:29 ` Joshua Clayton [this message]
2017-05-25 17:29 ` [PATCH v11 2/6] doc: dt: add altera-ps-spi binding document Joshua Clayton
2017-05-25 17:29 ` [PATCH v11 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs Joshua Clayton
2017-05-25 17:29 ` [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Joshua Clayton
2017-06-02 16:30   ` Andreas Färber
2017-06-02 19:39     ` stillcompiling at gmail.com
2017-06-02 19:54       ` Andreas Färber
2017-06-02 21:10         ` stillcompiling at gmail.com
2017-06-05 15:10           ` Alan Tull
2017-05-25 17:29 ` [PATCH v11 5/6] lib: add bitrev8x4() Joshua Clayton
2017-05-25 17:29 ` [PATCH v11 6/6] fpga-manager: altera-ps-spi: use bitrev8x4 Joshua Clayton
2017-06-02 15:49 ` [PATCH v11 0/6] FPGA Manager support for altera passive serial Anatolij Gustschin
2017-06-02 20:30 ` [PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed Joshua Clayton
2017-06-02 20:30   ` [PATCH v12 2/6] doc: dt: document altera-passive-serial binding Joshua Clayton
2017-06-05 15:11     ` Alan Tull
2017-06-02 20:30   ` [PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs Joshua Clayton
2017-06-05 15:11     ` Alan Tull
2017-06-02 20:30   ` [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Joshua Clayton
2017-06-05 15:12     ` Alan Tull
2017-06-02 20:30   ` [PATCH v12 5/6] lib: add bitrev8x4() Joshua Clayton
2017-06-05 15:12     ` Alan Tull
2017-06-02 20:30   ` [PATCH v12 6/6] fpga-manager: altera-ps-spi: use bitrev8x4 Joshua Clayton
2017-06-05 15:13     ` Alan Tull
2017-06-05 15:11   ` [PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed Alan Tull

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