* [PATCH v3 1/5] dt-bindings : Document the STM32F4 CRC32 binding [not found] <cover.1495463449.git.cosardindar@gmail.com> @ 2017-05-22 14:34 ` Cosar Dindar 2017-05-22 14:34 ` [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support Cosar Dindar ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Cosar Dindar @ 2017-05-22 14:34 UTC (permalink / raw) To: linux-arm-kernel Add device tree binding for STM32F4. Signed-off-by: Cosar Dindar <cosardindar@gmail.com> --- Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt index 3ba92a5..7b30f1e 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt @@ -1,7 +1,7 @@ * STMicroelectronics STM32 CRC Required properties: -- compatible: Should be "st,stm32f7-crc". +- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc". - reg: The address and length of the peripheral registers space - clocks: The input clock of the CRC instance @@ -10,7 +10,7 @@ Optional properties: none Example: crc: crc at 40023000 { - compatible = "st,stm32f7-crc"; + compatible = "st,stm32f7-crc", "st,stm32f4-crc"; reg = <0x40023000 0x400>; clocks = <&rcc 0 12>; }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support [not found] <cover.1495463449.git.cosardindar@gmail.com> 2017-05-22 14:34 ` [PATCH v3 1/5] dt-bindings : Document the STM32F4 CRC32 binding Cosar Dindar @ 2017-05-22 14:34 ` Cosar Dindar 2017-05-29 7:56 ` Fabien DESSENNE 2017-05-22 14:34 ` [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429 Cosar Dindar ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Cosar Dindar @ 2017-05-22 14:34 UTC (permalink / raw) To: linux-arm-kernel This patch adds CRC (CRC32 Crypto) support for STM32F4 series. As an hardware limitation polynomial and key setting are not supported. They are fixed as 0x4C11DB7 (poly) and 0xFFFFFFFF (key). CRC32C Castagnoli algorithm is not used. Signed-off-by: Cosar Dindar <cosardindar@gmail.com> --- drivers/crypto/stm32/stm32_crc32.c | 68 ++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c index ec83b1e..12fbd98 100644 --- a/drivers/crypto/stm32/stm32_crc32.c +++ b/drivers/crypto/stm32/stm32_crc32.c @@ -7,6 +7,7 @@ #include <linux/bitrev.h> #include <linux/clk.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <crypto/internal/hash.h> @@ -39,6 +40,9 @@ struct stm32_crc { struct clk *clk; u8 pending_data[sizeof(u32)]; size_t nb_pending_bytes; + bool key_support; + bool poly_support; + bool reverse_support; }; struct stm32_crc_list { @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc) } spin_unlock_bh(&crc_list.lock); - /* Reset, set key, poly and configure in bit reverse mode */ - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); + /* set key */ + if (ctx->crc->key_support) { + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); + } else if (mctx->key != CRC_INIT_DEFAULT) { + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 0x%x\n", + CRC_INIT_DEFAULT); + return -EINVAL; + } + + /* set poly */ + if (ctx->crc->poly_support) + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); + + /* reset and configure in bit reverse mode if supported */ + if (ctx->crc->reverse_support) + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); + else + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR); + + /* store partial result */ + if (!ctx->crc->reverse_support) + ctx->partial = bitrev32(readl(crc->regs + CRC_DR)); + else + ctx->partial = readl(ctx->crc->regs + CRC_DR); - /* Store partial result */ - ctx->partial = readl(ctx->crc->regs + CRC_DR); ctx->crc->nb_pending_bytes = 0; return 0; @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, if (crc->nb_pending_bytes == sizeof(u32)) { /* Process completed pending data */ - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR); + if (!ctx->crc->reverse_support) + writel(bitrev32(*(u32 *)crc->pending_data), + crc->regs + CRC_DR); + else + writel(*(u32 *)crc->pending_data, + crc->regs + CRC_DR); crc->nb_pending_bytes = 0; } } @@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, d32 = (u32 *)d8; for (i = 0; i < length >> 2; i++) /* Process 32 bits data */ - writel(*(d32++), crc->regs + CRC_DR); + if (!ctx->crc->reverse_support) + writel(bitrev32(*(d32++)), crc->regs + CRC_DR); + else + writel(*(d32++), crc->regs + CRC_DR); /* Store partial result */ - ctx->partial = readl(crc->regs + CRC_DR); + if (!ctx->crc->reverse_support) + ctx->partial = bitrev32(readl(crc->regs + CRC_DR)); + else + ctx->partial = readl(crc->regs + CRC_DR); /* Check for pending data (non 32 bits) */ length &= 3; @@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev) struct stm32_crc *crc; struct resource *res; int ret; + int algs_size; crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL); if (!crc) @@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev) return ret; } + /* set key, poly and reverse support if device is of F7 series */ + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) { + crc->key_support = true; + crc->poly_support = true; + crc->reverse_support = true; + } + platform_set_drvdata(pdev, crc); spin_lock(&crc_list.lock); list_add(&crc->list, &crc_list.dev_list); spin_unlock(&crc_list.lock); - ret = crypto_register_shashes(algs, ARRAY_SIZE(algs)); + /* For F4 series only CRC32 algorithm will be used */ + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc")) + algs_size = 1; + else + algs_size = ARRAY_SIZE(algs); + + ret = crypto_register_shashes(algs, algs_size); if (ret) { dev_err(dev, "Failed to register\n"); clk_disable_unprepare(crc->clk); @@ -304,6 +351,7 @@ static int stm32_crc_remove(struct platform_device *pdev) static const struct of_device_id stm32_dt_ids[] = { { .compatible = "st,stm32f7-crc", }, + { .compatible = "st,stm32f4-crc", }, {}, }; MODULE_DEVICE_TABLE(of, stm32_dt_ids); -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support 2017-05-22 14:34 ` [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support Cosar Dindar @ 2017-05-29 7:56 ` Fabien DESSENNE 2017-06-02 13:56 ` Cosar Dindar 0 siblings, 1 reply; 10+ messages in thread From: Fabien DESSENNE @ 2017-05-29 7:56 UTC (permalink / raw) To: linux-arm-kernel Hi Cosar, Thank you for the patch On 22/05/17 16:34, Cosar Dindar wrote: > This patch adds CRC (CRC32 Crypto) support for STM32F4 series. > > As an hardware limitation polynomial and key setting are not supported. > They are fixed as 0x4C11DB7 (poly) and 0xFFFFFFFF (key). > CRC32C Castagnoli algorithm is not used. > > Signed-off-by: Cosar Dindar <cosardindar@gmail.com> > --- > drivers/crypto/stm32/stm32_crc32.c | 68 ++++++++++++++++++++++++++++++++------ > 1 file changed, 58 insertions(+), 10 deletions(-) > > diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c > index ec83b1e..12fbd98 100644 > --- a/drivers/crypto/stm32/stm32_crc32.c > +++ b/drivers/crypto/stm32/stm32_crc32.c > @@ -7,6 +7,7 @@ > #include <linux/bitrev.h> > #include <linux/clk.h> > #include <linux/module.h> > +#include <linux/of.h> > #include <linux/platform_device.h> > > #include <crypto/internal/hash.h> > @@ -39,6 +40,9 @@ struct stm32_crc { > struct clk *clk; > u8 pending_data[sizeof(u32)]; > size_t nb_pending_bytes; > + bool key_support; > + bool poly_support; > + bool reverse_support; > }; > > struct stm32_crc_list { > @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc) > } > spin_unlock_bh(&crc_list.lock); > > - /* Reset, set key, poly and configure in bit reverse mode */ > - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); > - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); > - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); > + /* set key */ > + if (ctx->crc->key_support) { > + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); > + } else if (mctx->key != CRC_INIT_DEFAULT) { > + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 0x%x\n", > + CRC_INIT_DEFAULT); > + return -EINVAL; > + } > + > + /* set poly */ > + if (ctx->crc->poly_support) > + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); > + > + /* reset and configure in bit reverse mode if supported */ > + if (ctx->crc->reverse_support) > + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); > + else > + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR); > + > + /* store partial result */ > + if (!ctx->crc->reverse_support) > + ctx->partial = bitrev32(readl(crc->regs + CRC_DR)); > + else > + ctx->partial = readl(ctx->crc->regs + CRC_DR); > > - /* Store partial result */ > - ctx->partial = readl(ctx->crc->regs + CRC_DR); > ctx->crc->nb_pending_bytes = 0; > > return 0; > @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, > > if (crc->nb_pending_bytes == sizeof(u32)) { > /* Process completed pending data */ > - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR); > + if (!ctx->crc->reverse_support) > + writel(bitrev32(*(u32 *)crc->pending_data), > + crc->regs + CRC_DR); > + else > + writel(*(u32 *)crc->pending_data, > + crc->regs + CRC_DR); > crc->nb_pending_bytes = 0; > } > } > @@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, > d32 = (u32 *)d8; > for (i = 0; i < length >> 2; i++) > /* Process 32 bits data */ > - writel(*(d32++), crc->regs + CRC_DR); > + if (!ctx->crc->reverse_support) > + writel(bitrev32(*(d32++)), crc->regs + CRC_DR); > + else > + writel(*(d32++), crc->regs + CRC_DR); > > /* Store partial result */ > - ctx->partial = readl(crc->regs + CRC_DR); > + if (!ctx->crc->reverse_support) > + ctx->partial = bitrev32(readl(crc->regs + CRC_DR)); > + else > + ctx->partial = readl(crc->regs + CRC_DR); > > /* Check for pending data (non 32 bits) */ > length &= 3; > @@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev) > struct stm32_crc *crc; > struct resource *res; > int ret; > + int algs_size; > > crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL); > if (!crc) > @@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev) > return ret; > } > > + /* set key, poly and reverse support if device is of F7 series */ > + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) { > + crc->key_support = true; > + crc->poly_support = true; > + crc->reverse_support = true; > + } > + > platform_set_drvdata(pdev, crc); > > spin_lock(&crc_list.lock); > list_add(&crc->list, &crc_list.dev_list); > spin_unlock(&crc_list.lock); > > - ret = crypto_register_shashes(algs, ARRAY_SIZE(algs)); > + /* For F4 series only CRC32 algorithm will be used */ > + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc")) > + algs_size = 1; > + else > + algs_size = ARRAY_SIZE(algs); > + > + ret = crypto_register_shashes(algs, algs_size); > if (ret) { > dev_err(dev, "Failed to register\n"); > clk_disable_unprepare(crc->clk); > @@ -304,6 +351,7 @@ static int stm32_crc_remove(struct platform_device *pdev) > > static const struct of_device_id stm32_dt_ids[] = { > { .compatible = "st,stm32f7-crc", }, > + { .compatible = "st,stm32f4-crc", }, > {}, > }; > MODULE_DEVICE_TABLE(of, stm32_dt_ids); Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support 2017-05-29 7:56 ` Fabien DESSENNE @ 2017-06-02 13:56 ` Cosar Dindar 0 siblings, 0 replies; 10+ messages in thread From: Cosar Dindar @ 2017-06-02 13:56 UTC (permalink / raw) To: linux-arm-kernel Hi Fabien, Thanks for your review. On Mon, May 29, 2017 at 07:56:48AM +0000, Fabien DESSENNE wrote: > Hi Cosar, > > Thank you for the patch > > On 22/05/17 16:34, Cosar Dindar wrote: > > This patch adds CRC (CRC32 Crypto) support for STM32F4 series. > > > > As an hardware limitation polynomial and key setting are not supported. > > They are fixed as 0x4C11DB7 (poly) and 0xFFFFFFFF (key). > > CRC32C Castagnoli algorithm is not used. > > > > Signed-off-by: Cosar Dindar <cosardindar@gmail.com> > > --- > > drivers/crypto/stm32/stm32_crc32.c | 68 ++++++++++++++++++++++++++++++++------ > > 1 file changed, 58 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c > > index ec83b1e..12fbd98 100644 > > --- a/drivers/crypto/stm32/stm32_crc32.c > > +++ b/drivers/crypto/stm32/stm32_crc32.c > > @@ -7,6 +7,7 @@ > > #include <linux/bitrev.h> > > #include <linux/clk.h> > > #include <linux/module.h> > > +#include <linux/of.h> > > #include <linux/platform_device.h> > > > > #include <crypto/internal/hash.h> > > @@ -39,6 +40,9 @@ struct stm32_crc { > > struct clk *clk; > > u8 pending_data[sizeof(u32)]; > > size_t nb_pending_bytes; > > + bool key_support; > > + bool poly_support; > > + bool reverse_support; > > }; > > > > struct stm32_crc_list { > > @@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc) > > } > > spin_unlock_bh(&crc_list.lock); > > > > - /* Reset, set key, poly and configure in bit reverse mode */ > > - writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); > > - writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); > > - writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); > > + /* set key */ > > + if (ctx->crc->key_support) { > > + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); > > + } else if (mctx->key != CRC_INIT_DEFAULT) { > > + dev_err(ctx->crc->dev, "Unsupported key value! Should be: 0x%x\n", > > + CRC_INIT_DEFAULT); > > + return -EINVAL; > > + } > > + > > + /* set poly */ > > + if (ctx->crc->poly_support) > > + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); > > + > > + /* reset and configure in bit reverse mode if supported */ > > + if (ctx->crc->reverse_support) > > + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); > > + else > > + writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR); > > + > > + /* store partial result */ > > + if (!ctx->crc->reverse_support) > > + ctx->partial = bitrev32(readl(crc->regs + CRC_DR)); > > + else > > + ctx->partial = readl(ctx->crc->regs + CRC_DR); > > > > - /* Store partial result */ > > - ctx->partial = readl(ctx->crc->regs + CRC_DR); > > ctx->crc->nb_pending_bytes = 0; > > > > return 0; > > @@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, > > > > if (crc->nb_pending_bytes == sizeof(u32)) { > > /* Process completed pending data */ > > - writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR); > > + if (!ctx->crc->reverse_support) > > + writel(bitrev32(*(u32 *)crc->pending_data), > > + crc->regs + CRC_DR); > > + else > > + writel(*(u32 *)crc->pending_data, > > + crc->regs + CRC_DR); > > crc->nb_pending_bytes = 0; > > } > > } > > @@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, > > d32 = (u32 *)d8; > > for (i = 0; i < length >> 2; i++) > > /* Process 32 bits data */ > > - writel(*(d32++), crc->regs + CRC_DR); > > + if (!ctx->crc->reverse_support) > > + writel(bitrev32(*(d32++)), crc->regs + CRC_DR); > > + else > > + writel(*(d32++), crc->regs + CRC_DR); > > > > /* Store partial result */ > > - ctx->partial = readl(crc->regs + CRC_DR); > > + if (!ctx->crc->reverse_support) > > + ctx->partial = bitrev32(readl(crc->regs + CRC_DR)); > > + else > > + ctx->partial = readl(crc->regs + CRC_DR); > > > > /* Check for pending data (non 32 bits) */ > > length &= 3; > > @@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev) > > struct stm32_crc *crc; > > struct resource *res; > > int ret; > > + int algs_size; > > > > crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL); > > if (!crc) > > @@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev) > > return ret; > > } > > > > + /* set key, poly and reverse support if device is of F7 series */ > > + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) { > > + crc->key_support = true; > > + crc->poly_support = true; > > + crc->reverse_support = true; > > + } > > + > > platform_set_drvdata(pdev, crc); > > > > spin_lock(&crc_list.lock); > > list_add(&crc->list, &crc_list.dev_list); > > spin_unlock(&crc_list.lock); > > > > - ret = crypto_register_shashes(algs, ARRAY_SIZE(algs)); > > + /* For F4 series only CRC32 algorithm will be used */ > > + if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc")) > > + algs_size = 1; > > + else > > + algs_size = ARRAY_SIZE(algs); > > + > > + ret = crypto_register_shashes(algs, algs_size); > > if (ret) { > > dev_err(dev, "Failed to register\n"); > > clk_disable_unprepare(crc->clk); > > @@ -304,6 +351,7 @@ static int stm32_crc_remove(struct platform_device *pdev) > > > > static const struct of_device_id stm32_dt_ids[] = { > > { .compatible = "st,stm32f7-crc", }, > > + { .compatible = "st,stm32f4-crc", }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, stm32_dt_ids); > Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Best Regards. Cosar ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429 [not found] <cover.1495463449.git.cosardindar@gmail.com> 2017-05-22 14:34 ` [PATCH v3 1/5] dt-bindings : Document the STM32F4 CRC32 binding Cosar Dindar 2017-05-22 14:34 ` [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support Cosar Dindar @ 2017-05-22 14:34 ` Cosar Dindar 2017-05-23 13:59 ` Alexandre Torgue 2017-05-22 14:34 ` [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board Cosar Dindar 2017-05-22 14:35 ` [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board Cosar Dindar 4 siblings, 1 reply; 10+ messages in thread From: Cosar Dindar @ 2017-05-22 14:34 UTC (permalink / raw) To: linux-arm-kernel Add CRC32 Crypto support to stm32f429. Signed-off-by: Cosar Dindar <cosardindar@gmail.com> --- arch/arm/boot/dts/stm32f429.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index b2a2b5c..18343de 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -766,6 +766,13 @@ }; }; + crc: crc at 40023000 { + compatible = "st,stm32f4-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; + status = "disabled"; + }; + rcc: rcc at 40023810 { #reset-cells = <1>; #clock-cells = <2>; -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429 2017-05-22 14:34 ` [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429 Cosar Dindar @ 2017-05-23 13:59 ` Alexandre Torgue 0 siblings, 0 replies; 10+ messages in thread From: Alexandre Torgue @ 2017-05-23 13:59 UTC (permalink / raw) To: linux-arm-kernel On 05/22/2017 04:34 PM, Cosar Dindar wrote: > Add CRC32 Crypto support to stm32f429. > > Signed-off-by: Cosar Dindar <cosardindar@gmail.com> Will be applied in STM32 branch for next pull request. Thanks Alex > --- > arch/arm/boot/dts/stm32f429.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi > index b2a2b5c..18343de 100644 > --- a/arch/arm/boot/dts/stm32f429.dtsi > +++ b/arch/arm/boot/dts/stm32f429.dtsi > @@ -766,6 +766,13 @@ > }; > }; > > + crc: crc at 40023000 { > + compatible = "st,stm32f4-crc"; > + reg = <0x40023000 0x400>; > + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; > + status = "disabled"; > + }; > + > rcc: rcc at 40023810 { > #reset-cells = <1>; > #clock-cells = <2>; > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board [not found] <cover.1495463449.git.cosardindar@gmail.com> ` (2 preceding siblings ...) 2017-05-22 14:34 ` [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429 Cosar Dindar @ 2017-05-22 14:34 ` Cosar Dindar 2017-05-23 13:59 ` Alexandre Torgue 2017-05-22 14:35 ` [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board Cosar Dindar 4 siblings, 1 reply; 10+ messages in thread From: Cosar Dindar @ 2017-05-22 14:34 UTC (permalink / raw) To: linux-arm-kernel Enable the CRC32 crypto on stm32429-disco board. Signed-off-by: Cosar Dindar <cosardindar@gmail.com> --- arch/arm/boot/dts/stm32f429-disco.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 191fa50..ae47cde 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -102,6 +102,10 @@ clock-frequency = <8000000>; }; +&crc { + status = "okay"; +}; + &rtc { assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSI>; -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board 2017-05-22 14:34 ` [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board Cosar Dindar @ 2017-05-23 13:59 ` Alexandre Torgue 0 siblings, 0 replies; 10+ messages in thread From: Alexandre Torgue @ 2017-05-23 13:59 UTC (permalink / raw) To: linux-arm-kernel On 05/22/2017 04:34 PM, Cosar Dindar wrote: > Enable the CRC32 crypto on stm32429-disco board. > > Signed-off-by: Cosar Dindar <cosardindar@gmail.com> > --- Will be applied in STM32 branch for next pull request. Thanks Alex > arch/arm/boot/dts/stm32f429-disco.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts > index 191fa50..ae47cde 100644 > --- a/arch/arm/boot/dts/stm32f429-disco.dts > +++ b/arch/arm/boot/dts/stm32f429-disco.dts > @@ -102,6 +102,10 @@ > clock-frequency = <8000000>; > }; > > +&crc { > + status = "okay"; > +}; > + > &rtc { > assigned-clocks = <&rcc 1 CLK_RTC>; > assigned-clock-parents = <&rcc 1 CLK_LSI>; > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board [not found] <cover.1495463449.git.cosardindar@gmail.com> ` (3 preceding siblings ...) 2017-05-22 14:34 ` [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board Cosar Dindar @ 2017-05-22 14:35 ` Cosar Dindar 2017-05-23 13:59 ` Alexandre Torgue 4 siblings, 1 reply; 10+ messages in thread From: Cosar Dindar @ 2017-05-22 14:35 UTC (permalink / raw) To: linux-arm-kernel Enable the CRC32 crypto on stm32429i-eval board. Signed-off-by: Cosar Dindar <cosardindar@gmail.com> --- arch/arm/boot/dts/stm32429i-eval.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index b633114..360fb19 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -141,6 +141,10 @@ clock-frequency = <25000000>; }; +&crc { + status = "okay"; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board 2017-05-22 14:35 ` [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board Cosar Dindar @ 2017-05-23 13:59 ` Alexandre Torgue 0 siblings, 0 replies; 10+ messages in thread From: Alexandre Torgue @ 2017-05-23 13:59 UTC (permalink / raw) To: linux-arm-kernel On 05/22/2017 04:35 PM, Cosar Dindar wrote: > Enable the CRC32 crypto on stm32429i-eval board. > > Signed-off-by: Cosar Dindar <cosardindar@gmail.com> > --- Will be applied in STM32 branch for next pull request. Thanks Alex > arch/arm/boot/dts/stm32429i-eval.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts > index b633114..360fb19 100644 > --- a/arch/arm/boot/dts/stm32429i-eval.dts > +++ b/arch/arm/boot/dts/stm32429i-eval.dts > @@ -141,6 +141,10 @@ > clock-frequency = <25000000>; > }; > > +&crc { > + status = "okay"; > +}; > + > &i2c1 { > pinctrl-0 = <&i2c1_pins>; > pinctrl-names = "default"; > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-06-02 13:56 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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[not found] <cover.1495463449.git.cosardindar@gmail.com>
2017-05-22 14:34 ` [PATCH v3 1/5] dt-bindings : Document the STM32F4 CRC32 binding Cosar Dindar
2017-05-22 14:34 ` [PATCH v3 2/5] crypto : stm32 - Add STM32F4 CRC32 support Cosar Dindar
2017-05-29 7:56 ` Fabien DESSENNE
2017-06-02 13:56 ` Cosar Dindar
2017-05-22 14:34 ` [PATCH v3 3/5] ARM: dts: stm32: Add CRC support to stm32f429 Cosar Dindar
2017-05-23 13:59 ` Alexandre Torgue
2017-05-22 14:34 ` [PATCH v3 4/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board Cosar Dindar
2017-05-23 13:59 ` Alexandre Torgue
2017-05-22 14:35 ` [PATCH v3 5/5] ARM: dts: stm32: enable CRC32 on stm32429i-eval board Cosar Dindar
2017-05-23 13:59 ` Alexandre Torgue
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