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From: antoine.tenart@free-electrons.com (Antoine Tenart)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 1/5] Documentation/bindings: Document the SafeXel cryptographic engine driver
Date: Sun, 11 Jun 2017 10:53:53 +0200	[thread overview]
Message-ID: <20170611085353.GG31464@kwain> (raw)
In-Reply-To: <20170524141035.21031-2-antoine.tenart@free-electrons.com>

Hi Herbert,

On Wed, May 24, 2017 at 04:10:31PM +0200, Antoine Tenart wrote:
> The Inside Secure Safexcel cryptographic engine is found on some Marvell
> SoCs (7k/8k). Document the bindings used by its driver.
> 
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>

Since you applied the Safexcel crypto driver patch, I think you should
also apply this patch adding the corresponding bindings documentation.

Thanks!
Antoine

> ---
>  .../bindings/crypto/inside-secure-safexcel.txt     | 29 ++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
> 
> diff --git a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
> new file mode 100644
> index 000000000000..f69773f4252b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt
> @@ -0,0 +1,29 @@
> +Inside Secure SafeXcel cryptographic engine
> +
> +Required properties:
> +- compatible: Should be "inside-secure,safexcel-eip197".
> +- reg: Base physical address of the engine and length of memory mapped region.
> +- interrupts: Interrupt numbers for the rings and engine.
> +- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
> +
> +Optional properties:
> +- clocks: Reference to the crypto engine clock.
> +- dma-mask: The address mask limitation. Defaults to 64.
> +
> +Example:
> +
> +	crypto: crypto at 800000 {
> +		compatible = "inside-secure,safexcel-eip197";
> +		reg = <0x800000 0x200000>;
> +		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
> +				  "eip";
> +		clocks = <&cpm_syscon0 1 26>;
> +		dma-mask = <0xff 0xffffffff>;
> +		status = "disabled";
> +	};
> -- 
> 2.9.4
> 

-- 
Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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  reply	other threads:[~2017-06-11  8:53 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-24 14:10 [PATCH v6 0/5] arm64: marvell: add cryptographic engine support for 7k/8k Antoine Tenart
2017-05-24 14:10 ` [PATCH v6 1/5] Documentation/bindings: Document the SafeXel cryptographic engine driver Antoine Tenart
2017-06-11  8:53   ` Antoine Tenart [this message]
2017-06-20  3:37     ` Herbert Xu
2017-06-20  6:21       ` Antoine Tenart
2017-05-24 14:10 ` [PATCH v6 2/5] arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes Antoine Tenart
2017-05-24 15:13   ` Gregory CLEMENT
2017-05-24 14:10 ` [PATCH v6 3/5] arm64: marvell: dts: add dma-mask in crypto nodes for 7k/8k Antoine Tenart
2017-06-13  8:30   ` Gregory CLEMENT
2017-05-24 14:10 ` [PATCH v6 4/5] crypto: inside-secure: add SafeXcel EIP197 crypto engine driver Antoine Tenart
2017-05-28  5:39   ` PrasannaKumar Muralidharan
2017-05-29  9:21     ` Antoine Tenart
2017-05-29  9:42       ` PrasannaKumar Muralidharan
2017-06-10  4:16   ` Herbert Xu
2017-05-24 14:10 ` [PATCH v6 5/5] MAINTAINERS: add a maintainer for the Inside Secure crypto driver Antoine Tenart
2017-06-10  4:16   ` Herbert Xu

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