From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Tue, 27 Jun 2017 09:39:13 +0100 Subject: [PATCH v2 5/8] iommu/io-pgtable-arm: Support lockless operation In-Reply-To: <20170627051155.GA9525@virtx40> References: <20170623055326.GA2949@virtx40> <20170623085607.GC3718@virtx40> <7a8da378-19e2-2f35-877a-cc6ce389301a@arm.com> <20170623113405.GA5221@virtx40> <20170627051155.GA9525@virtx40> Message-ID: <20170627083912.GA5759@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Jun 27, 2017 at 10:41:55AM +0530, Linu Cherian wrote: > On Fri Jun 23, 2017 at 05:04:05PM +0530, Linu Cherian wrote: > > On Fri Jun 23, 2017 at 11:35:25AM +0100, Robin Murphy wrote: > > > Note that on a coherent platform like ThunderX that's as good as just > > > deleting it, because you'll never execute the case below. However, on > > > reflection I think it can at least safely be downgraded to dma_wmb() > > > (i.e. DMB) rather than a full DSB - would you be able to test what > > > difference that makes? > > > > The testing was done on Thunderx 1, which has a non coherent page table walk. > > Yes, downgrading to dma_wmb() helps. With this change, performance is back to v1. > > > > Should i send a patch for this ? I already did it: https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/commit/?h=for-joerg/arm-smmu/updates&id=77f3445866c39d8866b31d8d9fa47c7c20938e05 Will