From: horms@verge.net.au (Simon Horman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/7] ARM: dts: renesas: Add Inter Connect RAM
Date: Mon, 10 Jul 2017 10:40:11 +0200 [thread overview]
Message-ID: <20170710084010.GJ13680@verge.net.au> (raw)
In-Reply-To: <1499181798-28859-1-git-send-email-geert+renesas@glider.be>
On Tue, Jul 04, 2017 at 05:23:11PM +0200, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> R-Car Gen2 and RZ/G1 SoCs contain two or three blocks of SRAM, which can be
> used for several purposes. One such purpose is holding a jump stub for CPU
> core bringup.
>
> This patch series adds the SRAM blocks to the various DTS files, following
> the generic DT bindings for "mmio-sram" in
> Documentation/devicetree/bindings/sram/sram.txt. Reserving SRAM for jump
> stub for CPU core bringup will be handled in a follow-up series.
>
> Thanks!
Geert, these seem nice and clean to me.
Are they ready to be applied?
next prev parent reply other threads:[~2017-07-10 8:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-04 15:23 [PATCH 0/7] ARM: dts: renesas: Add Inter Connect RAM Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 1/7] ARM: dts: r8a7743: " Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 2/7] ARM: dts: r8a7745: " Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 3/7] ARM: dts: r8a7790: " Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 4/7] ARM: dts: r8a7791: " Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 5/7] ARM: dts: r8a7792: " Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 6/7] ARM: dts: r8a7793: " Geert Uytterhoeven
2017-07-04 15:23 ` [PATCH 7/7] ARM: dts: r8a7794: " Geert Uytterhoeven
2017-07-10 8:40 ` Simon Horman [this message]
2017-07-10 8:45 ` [PATCH 0/7] ARM: dts: renesas: " Geert Uytterhoeven
2017-07-10 9:26 ` Simon Horman
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