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From: viresh.kumar@linaro.org (Viresh Kumar)
To: linux-arm-kernel@lists.infradead.org
Subject: cpufreq: frequency scaling spec in DT node
Date: Wed, 12 Jul 2017 15:39:42 +0530	[thread overview]
Message-ID: <20170712100942.GF1679@vireshk-i7> (raw)
In-Reply-To: <9476e8ee-24ae-1676-067b-18a867892894@free.fr>

On 12-07-17, 11:58, Mason wrote:
> I would object to the characterization of "just a PLL" :-)
> 
> The PLL outputs "garbage" before actually "locking" a target
> frequency. It is not possible for the CPU to blindly change
> the PLL settings, because that crashes the system.
> 
> The bootloader implements the steps required to change said
> settings, so the strategy has been: have Linux use whatever
> PLL frequency the bootloader programs.
> 
> Behind the PLL, there is a glitch-free divider, which is able
> to divide the PLL output without crashing the system. I've
> been using that divider for DFS.
> 
> drivers/clk/clk-tango4.c

Okay, got it now.

Yes, you *really* need to create these OPPs dynamically. I am
convinced now :)

-- 
viresh

  reply	other threads:[~2017-07-12 10:09 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-29  9:48 cpufreq: frequency scaling spec in DT node Mason
2017-06-29 10:04 ` Viresh Kumar
2017-06-29 11:41   ` Mason
2017-06-29 13:01     ` Mason
2017-06-29 14:35       ` Viresh Kumar
2017-06-29 14:34     ` Viresh Kumar
2017-07-11  9:27       ` Mason
2017-07-11 10:25         ` Viresh Kumar
2017-07-11 11:09           ` Mason
2017-07-11 11:56             ` Mason
2017-07-12  3:41             ` Viresh Kumar
2017-07-12  9:58               ` Mason
2017-07-12 10:09                 ` Viresh Kumar [this message]
2017-07-12 11:25                   ` Mason
2017-07-12 14:08                     ` Viresh Kumar
2017-07-11 13:36         ` Mason
2017-07-12  3:56           ` Viresh Kumar

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