From mboxrd@z Thu Jan  1 00:00:00 1970
From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi)
Date: Thu, 13 Jul 2017 17:52:12 +0100
Subject: APM smmu implementation
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On Thu, Jul 13, 2017 at 09:08:38AM -0700, Feng Kan wrote:

[...]

> > Cavium are not using MMU-500 - the ThunderX SMMU is their own in-house
> > microarchitecture (with its own bugs and foibles), hence it rightly gets
> > its own implementation identifier. I think Lorenzo has plans to wire up
> > support for the IORT "Device memory address size limit" field, which is
> > the correct way for ACPI to describe the upstream bus width of your
> > MMU-500 integration (and all the other IOMMU integrations facing the
> > same issue).
> This is great, thanks.
> 
> Lorenzo, May I ask when will this be ready. We would very much like
> this change to push out into the latest CentOS release.

I should be able to post a patch at v4.13-rc1 aiming for v4.14.

Lorenzo