From: ard.biesheuvel@linaro.org (Ard Biesheuvel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/15] arm-soc: various: replace open coded VA->PA calculation of pen_release
Date: Sat, 5 Aug 2017 21:52:20 +0100 [thread overview]
Message-ID: <20170805205222.19868-14-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20170805205222.19868-1-ard.biesheuvel@linaro.org>
This replaces a few copies of the open coded calculations of the
physical address of 'pen_release' in the secondary startup code
of a couple of platforms.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm/mach-prima2/headsmp.S | 11 +++--------
arch/arm/mach-spear/headsmp.S | 11 +++--------
arch/arm/mach-sti/headsmp.S | 10 +++-------
arch/arm/plat-versatile/headsmp.S | 9 +--------
4 files changed, 10 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index 209d9fc5c16c..070df700bb38 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -9,6 +9,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
+
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
@@ -17,10 +19,7 @@
ENTRY(sirfsoc_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, pen_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -31,7 +30,3 @@ pen: ldr r7, [r6]
*/
b secondary_startup
ENDPROC(sirfsoc_secondary_startup)
-
- .align
-1: .long .
- .long pen_release
diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S
index c52192dc3d9f..4da01b103f33 100644
--- a/arch/arm/mach-spear/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
@@ -13,6 +13,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
+
__INIT
/*
@@ -23,10 +25,7 @@
ENTRY(spear13xx_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, pen_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -40,8 +39,4 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
-
- .align
-1: .long .
- .long pen_release
ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
index e0ad451700d5..cdf3442f397b 100644
--- a/arch/arm/mach-sti/headsmp.S
+++ b/arch/arm/mach-sti/headsmp.S
@@ -16,6 +16,8 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/assembler.h>
+
/*
* ST specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
@@ -24,10 +26,7 @@
ENTRY(sti_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, pen_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -38,6 +37,3 @@ pen: ldr r7, [r6]
*/
b secondary_startup
ENDPROC(sti_secondary_startup)
-
-1: .long .
- .long pen_release
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index 40f27e52de75..0f2a5eddac5a 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -21,10 +21,7 @@ ENTRY(versatile_secondary_startup)
ARM_BE8(setend be)
mrc p15, 0, r0, c0, c0, 5
bic r0, #0xff000000
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
+ adr_l r6, pen_release
pen: ldr r7, [r6]
cmp r7, r0
bne pen
@@ -34,8 +31,4 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
-
- .align
-1: .long .
- .long pen_release
ENDPROC(versatile_secondary_startup)
--
2.11.0
next prev parent reply other threads:[~2017-08-05 20:52 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-05 20:52 [PATCH 00/15] ARM: add and use convenience macros for PC relative references Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros Ard Biesheuvel
2017-08-08 15:10 ` Nicolas Pitre
2017-08-08 15:19 ` Ard Biesheuvel
2017-08-08 15:39 ` Nicolas Pitre
2017-08-05 20:52 ` [PATCH 02/15] ARM: head-common.S: use PC-relative insn sequence for __proc_info Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 03/15] ARM: head-common.S: use PC-relative insn sequence for __turn_mmu_on Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 04/15] ARM: head.S: use PC-relative insn sequence for secondary_data Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 05/15] ARM: head: use PC-relative insn sequence for __smp_alt Ard Biesheuvel
2017-08-11 15:13 ` Tony Lindgren
2017-08-11 19:37 ` Ard Biesheuvel
2017-08-11 19:58 ` Nicolas Pitre
2017-08-11 20:01 ` Ard Biesheuvel
2017-08-11 20:06 ` Nicolas Pitre
2017-08-11 20:07 ` Ard Biesheuvel
2017-08-11 20:12 ` Nicolas Pitre
2017-08-14 16:19 ` Tony Lindgren
2017-08-14 16:20 ` Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 06/15] ARM: sleep.S: use PC-relative insn sequence for sleep_save_sp/mpidr_hash Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 07/15] ARM: head.S: use PC-relative insn sequences for __fixup_pv_table Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 08/15] ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 09/15] ARM: kvm: replace open coded VA->PA calculations with adr_l call Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 10/15] arm-soc: exynos: replace open coded VA->PA conversions Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 11/15] arm-soc: mvebu: replace open coded VA->PA conversion Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations Ard Biesheuvel
2017-08-09 19:05 ` Tony Lindgren
2017-08-09 19:22 ` Ard Biesheuvel
2017-08-09 21:05 ` Tony Lindgren
2017-08-10 9:22 ` Ard Biesheuvel
2017-08-10 14:03 ` Tony Lindgren
2017-08-11 13:48 ` Ard Biesheuvel
2017-08-11 15:00 ` Tony Lindgren
2017-08-05 20:52 ` Ard Biesheuvel [this message]
2017-08-05 20:52 ` [PATCH 14/15] arm-soc: shmobile: replace open coded VA->PA calculation Ard Biesheuvel
2017-08-05 20:52 ` [PATCH 15/15] ARM: l2c: " Ard Biesheuvel
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