From: ard.biesheuvel@linaro.org (Ard Biesheuvel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 17/30] arm-soc: tegra: make sleep asm code runtime relocatable
Date: Mon, 14 Aug 2017 13:53:58 +0100 [thread overview]
Message-ID: <20170814125411.22604-18-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20170814125411.22604-1-ard.biesheuvel@linaro.org>
The PIE kernel build does not allow absolute references encoded in
movw/movt instruction pairs, so use our mov_l macro instead (which
will still use such a pair unless CONFIG_RELOCATABLE is defined)
Also, avoid 32-bit absolute literals to refer to absolute symbols.
Instead, use a 16 bit reference so that PIE linker cannot get
confused whether the symbol reference is subject to relocation at
runtime.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm/mach-tegra/sleep-tegra20.S | 22 ++++++++++++--------
arch/arm/mach-tegra/sleep-tegra30.S | 6 +++---
arch/arm/mach-tegra/sleep.S | 4 ++--
3 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 5c8e638ee51a..cab95de5c8f1 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -99,7 +99,7 @@ ENTRY(tegra20_cpu_shutdown)
cmp r0, #0
reteq lr @ must not be called for CPU 0
mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
+ ldrh r2, 0f
mov r12, #CPU_RESETTABLE
strb r12, [r1, r2]
@@ -121,6 +121,7 @@ ENTRY(tegra20_cpu_shutdown)
beq .
ret lr
ENDPROC(tegra20_cpu_shutdown)
+0: .short __tegra20_cpu1_resettable_status_offset
#endif
#ifdef CONFIG_PM_SLEEP
@@ -181,6 +182,9 @@ ENTRY(tegra_pen_unlock)
ret lr
ENDPROC(tegra_pen_unlock)
+.L__tegra20_cpu1_resettable_status_offset:
+ .short __tegra20_cpu1_resettable_status_offset
+
/*
* tegra20_cpu_clear_resettable(void)
*
@@ -189,7 +193,7 @@ ENDPROC(tegra_pen_unlock)
*/
ENTRY(tegra20_cpu_clear_resettable)
mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
+ ldrh r2, .L__tegra20_cpu1_resettable_status_offset
mov r12, #CPU_NOT_RESETTABLE
strb r12, [r1, r2]
ret lr
@@ -203,7 +207,7 @@ ENDPROC(tegra20_cpu_clear_resettable)
*/
ENTRY(tegra20_cpu_set_resettable_soon)
mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
+ ldrh r2, .L__tegra20_cpu1_resettable_status_offset
mov r12, #CPU_RESETTABLE_SOON
strb r12, [r1, r2]
ret lr
@@ -217,7 +221,7 @@ ENDPROC(tegra20_cpu_set_resettable_soon)
*/
ENTRY(tegra20_cpu_is_resettable_soon)
mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
+ ldrh r2, .L__tegra20_cpu1_resettable_status_offset
ldrb r12, [r1, r2]
cmp r12, #CPU_RESETTABLE_SOON
moveq r0, #1
@@ -238,11 +242,11 @@ ENTRY(tegra20_sleep_core_finish)
bl tegra_disable_clean_inv_dcache
mov r0, r4
- mov32 r3, tegra_shut_off_mmu
+ mov_l r3, tegra_shut_off_mmu
add r3, r3, r0
- mov32 r0, tegra20_tear_down_core
- mov32 r1, tegra20_iram_start
+ mov_l r0, tegra20_tear_down_core
+ mov_l r1, tegra20_iram_start
sub r0, r0, r1
mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
add r0, r0, r1
@@ -265,7 +269,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
bl tegra_disable_clean_inv_dcache
mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r4, =__tegra20_cpu1_resettable_status_offset
+ ldrh r4, .L__tegra20_cpu1_resettable_status_offset
mov r3, #CPU_RESETTABLE
strb r3, [r0, r4]
@@ -284,7 +288,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
bl tegra_pen_lock
mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r4, =__tegra20_cpu1_resettable_status_offset
+ ldrh r4, .L__tegra20_cpu1_resettable_status_offset
mov r3, #CPU_NOT_RESETTABLE
strb r3, [r0, r4]
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index dd4a67dabd91..478b2ca3ef6e 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -261,11 +261,11 @@ ENTRY(tegra30_sleep_core_finish)
mov32 r6, TEGRA_FLOW_CTRL_BASE
mov32 r7, TEGRA_TMRUS_BASE
- mov32 r3, tegra_shut_off_mmu
+ mov_l r3, tegra_shut_off_mmu
add r3, r3, r0
- mov32 r0, tegra30_tear_down_core
- mov32 r1, tegra30_iram_start
+ mov_l r0, tegra30_tear_down_core
+ mov_l r1, tegra30_iram_start
sub r0, r0, r1
mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
add r0, r0, r1
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 5e3496753df1..785df3edc767 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -101,11 +101,11 @@ ENTRY(tegra_sleep_cpu_finish)
bl tegra_disable_clean_inv_dcache
mov r0, r4
- mov32 r6, tegra_tear_down_cpu
+ mov_l r6, tegra_tear_down_cpu
ldr r1, [r6]
add r1, r1, r0
- mov32 r3, tegra_shut_off_mmu
+ mov_l r3, tegra_shut_off_mmu
add r3, r3, r0
mov r0, r1
--
2.11.0
next prev parent reply other threads:[~2017-08-14 12:53 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-14 12:53 [PATCH 00/30] implement KASLR for ARM Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 01/30] asm-generic: add .data.rel.ro sections to __ro_after_init Ard Biesheuvel
2017-08-14 14:26 ` Arnd Bergmann
2017-08-14 12:53 ` [PATCH 02/30] ARM: assembler: introduce adr_l, ldr_l and str_l macros Ard Biesheuvel
2017-08-14 15:29 ` Dave Martin
2017-08-14 15:38 ` Ard Biesheuvel
2017-08-14 15:50 ` Dave Martin
2017-08-14 16:18 ` Nicolas Pitre
2017-08-14 16:22 ` Ard Biesheuvel
2017-08-14 16:33 ` Nicolas Pitre
2017-08-14 16:42 ` Russell King - ARM Linux
2017-08-14 16:56 ` Ard Biesheuvel
2017-08-14 15:32 ` Dave Martin
2017-08-14 15:40 ` Ard Biesheuvel
2017-08-14 15:53 ` Dave Martin
2017-08-14 12:53 ` [PATCH 03/30] ARM: head-common.S: use PC-relative insn sequence for __proc_info Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 04/30] ARM: head-common.S: use PC-relative insn sequence for idmap creation Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 05/30] ARM: head.S: use PC-relative insn sequence for secondary_data Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 06/30] ARM: kernel: use relative references for UP/SMP alternatives Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 07/30] ARM: head: use PC-relative insn sequence for __smp_alt Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 08/30] ARM: sleep.S: use PC-relative insn sequence for sleep_save_sp/mpidr_hash Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 09/30] ARM: head.S: use PC-relative insn sequences for __fixup_pv_table Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 10/30] ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 11/30] ARM: kvm: replace open coded VA->PA calculations with adr_l call Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 12/30] arm-soc: exynos: replace open coded VA->PA conversions Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 13/30] arm-soc: mvebu: replace open coded VA->PA conversion Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 14/30] arm-soc: various: replace open coded VA->PA calculation of pen_release Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 15/30] ARM: kernel: switch to relative exception tables Ard Biesheuvel
2017-08-14 12:53 ` [PATCH 16/30] ARM: kernel: use relative phys-to-virt patch tables Ard Biesheuvel
2017-08-14 12:53 ` Ard Biesheuvel [this message]
2017-08-14 14:42 ` [PATCH 17/30] arm-soc: tegra: make sleep asm code runtime relocatable Dave Martin
2017-08-14 14:49 ` Ard Biesheuvel
2017-08-14 15:29 ` Dave Martin
2017-08-14 12:53 ` [PATCH 18/30] ARM: kernel: make vmlinux buildable as a PIE executable Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 19/30] ARM: kernel: use PC-relative symbol references in MMU switch code Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 20/30] ARM: kernel: use PC relative symbol references in suspend/resume code Ard Biesheuvel
2017-08-14 16:02 ` Nicolas Pitre
2017-08-14 18:14 ` Ard Biesheuvel
2017-08-14 18:37 ` Nicolas Pitre
2017-08-14 12:54 ` [PATCH 21/30] ARM: mm: export default vmalloc base address Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 22/30] ARM: kernel: refer to swapper_pg_dir via its symbol Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 23/30] ARM: kernel: implement randomization of the kernel load address Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 24/30] ARM: decompressor: explicitly map decompressor binary cacheable Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 25/30] ARM: compressed: factor out zImage header and make it extensible Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 26/30] ARM: decompressor: add KASLR support Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 27/30] efi/libstub: add 'max' parameter to efi_random_alloc() Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 28/30] efi/libstub: check for vmalloc= command line argument Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 29/30] efi/libstub: arm: reserve bootloader supplied initrd in memory map Ard Biesheuvel
2017-08-18 11:48 ` Ard Biesheuvel
2017-08-21 10:37 ` Mark Rutland
2017-08-21 10:39 ` Ard Biesheuvel
2017-08-14 12:54 ` [PATCH 30/30] efi/libstub: arm: implement KASLR Ard Biesheuvel
2017-08-14 15:30 ` [PATCH 00/30] implement KASLR for ARM Arnd Bergmann
2017-08-14 15:49 ` Ard Biesheuvel
2017-08-14 16:03 ` Arnd Bergmann
2017-08-14 16:28 ` Nicolas Pitre
2017-08-14 17:28 ` Ard Biesheuvel
2017-08-14 18:01 ` Nicolas Pitre
2017-08-14 18:08 ` Ard Biesheuvel
2017-08-14 16:16 ` Nicolas Pitre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170814125411.22604-18-ard.biesheuvel@linaro.org \
--to=ard.biesheuvel@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).