[RESEND PATCH 0/2] Enable SPI on A64/Pine64

[RESEND PATCH 0/2] Enable SPI on A64/Pine64

[Stefan Brüns]

The A64 SPI controller is compatible to the H3/H5 controller, i.e. same
registers and same queue depth.

The Pine64 exposes both controllers on the PI-2 and Euler connectors.

Tested/verified with logic analyser and spidev_test using MOSI/MISO loopback.

Note: spi0 on the A64 may conflict with the eMMC controller, as the MISO pin is
also used for the HS400 eMMC data strobe. This is only a concern if the board
uses eMMC (does not apply to the Pine64) *and* is using HS400 mode. The same
pin conflict exists for the H5.

Stefan Br?ns (2):
  arm64: allwinner: a64: add SPI nodes
  arm64: allwinner: pine64: Enable spi0/spi1

 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |  8 +++++
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      | 40 ++++++++++++++++++++++
 2 files changed, 48 insertions(+)

-- 
2.14.1

[RESEND PATCH 1/2] arm64: allwinner: a64: add SPI nodes

[Stefan Brüns]

The A64 SPI controllers are register compatible to the h3/h5 SPI
controllers.

The A64 has two SPI controllers, each with a single chip select.
The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
as the A64 DMA controller node is currently missing.

Signed-off-by: Stefan Br?ns <stefan.bruens@rwth-aachen.de>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index bd0f33b77f57..373cd14f0206 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -325,6 +325,16 @@
 				drive-strength = <40>;
 			};
 
+			spi0_pins: spi0 {
+				pins = "PC0", "PC1", "PC2", "PC3";
+				function = "spi0";
+			};
+
+			spi1_pins: spi1 {
+				pins = "PD0", "PD1", "PD2", "PD3";
+				function = "spi1";
+			};
+
 			uart0_pins_a: uart0 at 0 {
 				pins = "PB8", "PB9";
 				function = "uart0";
@@ -527,5 +537,35 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
+
+		spi0: spi at 01c68000 {
+			compatible = "allwinner,sun8i-h3-spi";
+			reg = <0x01c68000 0x1000>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+			clock-names = "ahb", "mod";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi0_pins>;
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi at 01c69000 {
+			compatible = "allwinner,sun8i-h3-spi";
+			reg = <0x01c69000 0x1000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+			clock-names = "ahb", "mod";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
-- 
2.14.1

[RESEND PATCH 2/2] arm64: allwinner: pine64: Enable spi0/spi1

[Stefan Brüns]

The two spi channels/controllers are available on the PI-2 resp. Euler
connector, enable both. Contrary to the Pi, the A64 SOC only supports
one chip select, so the second chipselect is not available (though
it can be emulated using gpio chipselect).

Signed-off-by: Stefan Br?ns <stefan.bruens@rwth-aachen.de>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 827168bc22ed..f25274e8b3e0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -124,6 +124,14 @@
 	status = "okay";
 };
 
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
 /* On Exp and Euler connectors */
 &uart0 {
 	pinctrl-names = "default";
-- 
2.14.1

[RESEND PATCH 1/2] arm64: allwinner: a64: add SPI nodes

[Maxime Ripard]

Hi Stefan,

On Tue, Aug 29, 2017 at 10:26:51PM +0200, Stefan Br?ns wrote:
> The A64 SPI controllers are register compatible to the h3/h5 SPI
> controllers.
> 
> The A64 has two SPI controllers, each with a single chip select.
> The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
> as the A64 DMA controller node is currently missing.
> 
> Signed-off-by: Stefan Br?ns <stefan.bruens@rwth-aachen.de>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index bd0f33b77f57..373cd14f0206 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -325,6 +325,16 @@
>  				drive-strength = <40>;
>  			};
>  
> +			spi0_pins: spi0 {
> +				pins = "PC0", "PC1", "PC2", "PC3";
> +				function = "spi0";
> +			};
> +
> +			spi1_pins: spi1 {
> +				pins = "PD0", "PD1", "PD2", "PD3";
> +				function = "spi1";
> +			};
> +
>  			uart0_pins_a: uart0 at 0 {
>  				pins = "PB8", "PB9";
>  				function = "uart0";
> @@ -527,5 +537,35 @@
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  		};
> +
> +		spi0: spi at 01c68000 {
> +			compatible = "allwinner,sun8i-h3-spi";
> +			reg = <0x01c68000 0x1000>;
> +			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> +			clock-names = "ahb", "mod";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&spi0_pins>;
> +			resets = <&ccu RST_BUS_SPI0>;
> +			status = "disabled";
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi1: spi at 01c69000 {
> +			compatible = "allwinner,sun8i-h3-spi";
> +			reg = <0x01c69000 0x1000>;
> +			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> +			clock-names = "ahb", "mod";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&spi1_pins>;
> +			resets = <&ccu RST_BUS_SPI1>;
> +			status = "disabled";
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};

Those nodes are ordered by ascending physical base address, so they
belong a bit above were you placed them.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[RESEND PATCH 2/2] arm64: allwinner: pine64: Enable spi0/spi1

[Maxime Ripard]

Hi Stefan,

On Tue, Aug 29, 2017 at 10:26:52PM +0200, Stefan Br?ns wrote:
> The two spi channels/controllers are available on the PI-2 resp. Euler
> connector, enable both. Contrary to the Pi, the A64 SOC only supports
> one chip select, so the second chipselect is not available (though
> it can be emulated using gpio chipselect).
> 
> Signed-off-by: Stefan Br?ns <stefan.bruens@rwth-aachen.de>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> index 827168bc22ed..f25274e8b3e0 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> @@ -124,6 +124,14 @@
>  	status = "okay";
>  };
>  
> +&spi0 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +};

Anything on the Euler or PI connector is muxable to some other
function. We cannot enforce a default, since we can't know for sure
that all our users will use it that way (even though the majority
probably will). This is why you also have those nodes populated but
disabled for the uart for example in the pine64 DTS.

But in our case, there's not much to populate :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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