From: cdall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 16/21] KVM: arm64: Save/Restore guest DISR_EL1
Date: Tue, 31 Oct 2017 06:27:15 +0100 [thread overview]
Message-ID: <20171031052715.GA129057@lvm> (raw)
In-Reply-To: <20171019145807.23251-17-james.morse@arm.com>
On Thu, Oct 19, 2017 at 03:58:02PM +0100, James Morse wrote:
> If we deliver a virtual SError to the guest, the guest may defer it
> with an ESB instruction. The guest reads the deferred value via DISR_EL1,
> but the guests view of DISR_EL1 is re-mapped to VDISR_EL2 when HCR_EL2.AMO
> is set.
>
> Add the KVM code to save/restore VDISR_EL2, and make it accessible to
> userspace as DISR_EL1.
>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> arch/arm64/include/asm/kvm_host.h | 1 +
> arch/arm64/include/asm/sysreg.h | 1 +
> arch/arm64/kvm/hyp/sysreg-sr.c | 6 ++++++
> arch/arm64/kvm/sys_regs.c | 1 +
> 4 files changed, 9 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 28a4de85edee..97438cc3a9ad 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -120,6 +120,7 @@ enum vcpu_sysreg {
> PAR_EL1, /* Physical Address Register */
> MDSCR_EL1, /* Monitor Debug System Control Register */
> MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
> + DISR_EL1, /* Deferred Interrupt Status Register */
>
> /* Performance Monitors Registers */
> PMCR_EL0, /* Control Register */
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index a493e93de296..1b8b9012234d 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -256,6 +256,7 @@
> #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
> #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
>
> +#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
> #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
> #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
> #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
> index 934137647837..f4d604803b29 100644
> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> @@ -66,6 +66,9 @@ static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
> ctxt->gp_regs.sp_el1 = read_sysreg(sp_el1);
> ctxt->gp_regs.elr_el1 = read_sysreg_el1(elr);
> ctxt->gp_regs.spsr[KVM_SPSR_EL1]= read_sysreg_el1(spsr);
> +
> + if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
> + ctxt->sys_regs[DISR_EL1] = read_sysreg_s(SYS_VDISR_EL2);
> }
>
> static hyp_alternate_select(__sysreg_call_save_host_state,
> @@ -119,6 +122,9 @@ static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
> write_sysreg(ctxt->gp_regs.sp_el1, sp_el1);
> write_sysreg_el1(ctxt->gp_regs.elr_el1, elr);
> write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr);
> +
> + if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
> + write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2);
> }
>
> static hyp_alternate_select(__sysreg_call_restore_host_state,
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2e070d3baf9f..713275b501ce 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -963,6 +963,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
>
> { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
> + { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
>
> { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
> { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
> --
> 2.13.3
>
next prev parent reply other threads:[~2017-10-31 5:27 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-19 14:57 [PATCH v4 00/21] SError rework + RAS&IESB for firmware first support James Morse
2017-10-19 14:57 ` [PATCH v4 01/21] arm64: explicitly mask all exceptions James Morse
2017-10-19 14:57 ` [PATCH v4 02/21] arm64: introduce an order for exceptions James Morse
2017-10-19 14:57 ` [PATCH v4 03/21] arm64: Move the async/fiq helpers to explicitly set process context flags James Morse
2017-10-19 14:57 ` [PATCH v4 04/21] arm64: Mask all exceptions during kernel_exit James Morse
2017-10-19 14:57 ` [PATCH v4 05/21] arm64: entry.S: Remove disable_dbg James Morse
2017-10-19 14:57 ` [PATCH v4 06/21] arm64: entry.S: convert el1_sync James Morse
2017-10-19 14:57 ` [PATCH v4 07/21] arm64: entry.S convert el0_sync James Morse
2017-10-19 14:57 ` [PATCH v4 08/21] arm64: entry.S: convert elX_irq James Morse
2017-10-19 14:57 ` [PATCH v4 09/21] KVM: arm/arm64: mask/unmask daif around VHE guests James Morse
2017-10-30 7:40 ` Christoffer Dall
2017-11-02 12:14 ` James Morse
2017-11-03 12:45 ` Christoffer Dall
2017-11-03 17:19 ` James Morse
2017-11-06 12:42 ` Christoffer Dall
2017-10-19 14:57 ` [PATCH v4 10/21] arm64: entry.S: move SError handling into a C function for future expansion James Morse
2018-01-02 21:07 ` Adam Wallis
2018-01-03 16:00 ` James Morse
2017-10-19 14:57 ` [PATCH v4 11/21] arm64: cpufeature: Detect CPU RAS Extentions James Morse
2017-10-31 13:14 ` Will Deacon
2017-11-02 12:15 ` James Morse
2017-10-19 14:57 ` [PATCH v4 12/21] arm64: kernel: Survive corrected RAS errors notified by SError James Morse
2017-10-31 13:50 ` Will Deacon
2017-11-02 12:15 ` James Morse
2017-10-19 14:57 ` [PATCH v4 13/21] arm64: cpufeature: Enable IESB on exception entry/return for firmware-first James Morse
2017-10-31 13:56 ` Will Deacon
2017-10-19 14:58 ` [PATCH v4 14/21] arm64: kernel: Prepare for a DISR user James Morse
2017-10-19 14:58 ` [PATCH v4 15/21] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2 James Morse
2017-10-20 16:44 ` gengdongjiu
2017-10-23 15:26 ` James Morse
2017-10-24 9:53 ` gengdongjiu
2017-10-30 7:59 ` Christoffer Dall
2017-10-30 10:51 ` Christoffer Dall
2017-10-30 15:44 ` James Morse
2017-10-31 5:48 ` Christoffer Dall
2017-10-31 6:34 ` Marc Zyngier
2017-10-19 14:58 ` [PATCH v4 16/21] KVM: arm64: Save/Restore guest DISR_EL1 James Morse
2017-10-31 4:27 ` Marc Zyngier
2017-10-31 5:27 ` Christoffer Dall [this message]
2017-10-19 14:58 ` [PATCH v4 17/21] KVM: arm64: Save ESR_EL2 on guest SError James Morse
2017-10-31 4:26 ` Marc Zyngier
2017-10-31 5:47 ` Marc Zyngier
2017-11-01 17:42 ` James Morse
2017-10-19 14:58 ` [PATCH v4 18/21] KVM: arm64: Handle RAS SErrors from EL1 on guest exit James Morse
2017-10-31 5:55 ` Marc Zyngier
2017-10-31 5:56 ` Christoffer Dall
2017-10-19 14:58 ` [PATCH v4 19/21] KVM: arm64: Handle RAS SErrors from EL2 " James Morse
2017-10-27 6:26 ` gengdongjiu
2017-10-27 17:38 ` James Morse
2017-10-31 6:13 ` Marc Zyngier
2017-10-31 6:13 ` Christoffer Dall
2017-10-19 14:58 ` [PATCH v4 20/21] KVM: arm64: Take any host SError before entering the guest James Morse
2017-10-31 6:23 ` Christoffer Dall
2017-10-31 11:43 ` James Morse
2017-11-01 4:55 ` Christoffer Dall
2017-11-02 12:18 ` James Morse
2017-11-03 12:49 ` Christoffer Dall
2017-11-03 16:14 ` James Morse
2017-11-06 12:45 ` Christoffer Dall
2017-10-19 14:58 ` [PATCH v4 21/21] KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA James Morse
2017-10-31 6:32 ` Christoffer Dall
2017-10-31 6:32 ` Marc Zyngier
2017-10-31 6:35 ` [PATCH v4 00/21] SError rework + RAS&IESB for firmware first support Christoffer Dall
2017-10-31 10:08 ` Will Deacon
2017-11-01 15:23 ` James Morse
2017-11-02 8:14 ` Christoffer Dall
2017-11-09 18:14 ` James Morse
2017-11-10 12:03 ` gengdongjiu
2017-11-13 11:29 ` Christoffer Dall
2017-11-13 13:05 ` Peter Maydell
2017-11-20 8:53 ` Christoffer Dall
2017-11-13 16:14 ` Andrew Jones
2017-11-13 17:56 ` Peter Maydell
2017-11-14 16:11 ` James Morse
2017-11-15 9:59 ` gengdongjiu
2017-11-14 16:03 ` James Morse
2017-11-15 9:15 ` gengdongjiu
2017-11-15 18:25 ` James Morse
2017-11-21 11:31 ` gengdongjiu
2017-11-20 8:55 ` Christoffer Dall
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171031052715.GA129057@lvm \
--to=cdall@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).