From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Sat, 18 Nov 2017 13:48:41 +0000 Subject: [PATCH 01/11] Initialize the mapping of KASan shadow memory In-Reply-To: References: <8e959f69-a578-793b-6c32-18b5b0cd08c2@arm.com> <87a7znsubp.fsf@on-the-bus.cambridge.arm.com> <87po8ir1kg.fsf@on-the-bus.cambridge.arm.com> <87375eqobb.fsf@on-the-bus.cambridge.arm.com> <20171117073556.GB28855@cbox> Message-ID: <20171118134841.3f6c9183@why.wild-wind.fr.eu.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sat, 18 Nov 2017 10:40:08 +0000 "Liuwenliang (Abbott Liu)" wrote: > On Nov 17, 2017 15:36 Christoffer Dall [mailto:cdall at linaro.org] wrote: > >If your processor does support LPAE (like a Cortex-A15 for example), > >then you have both the 32-bit accessors (MRC and MCR) and the 64-bit > >accessors (MRRC, MCRR), and using the 32-bit accessor will simply access > >the lower 32-bits of the 64-bit register. > > > >Hope this helps, > >-Christoffer > > If you know the higher 32-bits of the 64-bits cp15's register is not useful for your system, > then you can use the 32-bit accessor to get or set the 64-bit cp15's register. > But if the higher 32-bits of the 64-bits cp15's register is useful for your system, > then you can't use the 32-bit accessor to get or set the 64-bit cp15's register. > > TTBR0/TTBR1/PAR's higher 32-bits is useful for CPU supporting LPAE. > The following description which comes from ARM(r) Architecture Reference > Manual ARMv7-A and ARMv7-R edition tell us the reason: > > 64-bit TTBR0 and TTBR1 format: > ... > BADDR, bits[39:x] : > Translation table base address, bits[39:x]. Defining the translation table base address width on > page B4-1698 describes how x is defined. > The value of x determines the required alignment of the translation table, which must be aligned to > 2x bytes. > > Abbott Liu: Because BADDR on CPU supporting LPAE may be bigger than max value of 32-bit, so bits[39:32] may > be valid value which is useful for the system. > > 64-bit PAR format > ... > PA[39:12] > Physical Address. The physical address corresponding to the supplied virtual address. This field > returns address bits[39:12]. > > Abbott Liu: Because Physical Address on CPU supporting LPAE may be bigger than max value of 32-bit, > so bits[39:32] may be valid value which is useful for the system. > > Conclusion: Don't use 32-bit accessor to get or set TTBR0/TTBR1/PAR on CPU supporting LPAE, > if you do that, your system may run error. That's not really true. You can run an non-LPAE kernel that uses the 32bit accessors an a Cortex-A15 that supports LPAE. You're just limited to 4GB of physical space. And you're pretty much guaranteed to have some memory below 4GB (one way or another), or you'd have a slight problem setting up your page tables. M. -- Without deviation from the norm, progress is not possible.