From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 14/18] arm64: erratum: Work around Falkor erratum #E1003 in trampoline code
Date: Mon, 20 Nov 2017 18:05:49 +0000 [thread overview]
Message-ID: <20171120180548.GL32488@arm.com> (raw)
In-Reply-To: <20171118002714.GC18379@codeaurora.org>
On Fri, Nov 17, 2017 at 04:27:14PM -0800, Stephen Boyd wrote:
> On 11/17, Will Deacon wrote:
> > We rely on an atomic swizzling of TTBR1 when transitioning from the entry
> > trampoline to the kernel proper on an exception. We can't rely on this
> > atomicity in the face of Falkor erratum #E1003, so on affected cores we
> > can issue a TLB invalidation prior to jumping into the kernel. There is
> > still the possibility of a TLB conflict here due to conflicting walk
> > cache entries, but this doesn't appear to be the case on these CPUs in
> > practice.
> >
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
> > ---
> > arch/arm64/Kconfig | 17 +++++------------
> > arch/arm64/kernel/entry.S | 8 ++++++++
> > 2 files changed, 13 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > index 0df64a6a56d4..f0fcbfc2262e 100644
> > --- a/arch/arm64/Kconfig
> > +++ b/arch/arm64/Kconfig
> > @@ -504,20 +504,13 @@ config CAVIUM_ERRATUM_30115
> > config QCOM_FALKOR_ERRATUM_1003
> > bool "Falkor E1003: Incorrect translation due to ASID change"
> > default y
> > - select ARM64_PAN if ARM64_SW_TTBR0_PAN
>
> Cool, this sort of complicates the backport of the Kryo MIDR
> update of this errata to stable trees though.
Yeah, you may have to do a separate version for -stable if you don't
want to backport parts of this series.
> > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> > index a839b94bba05..a600879939ce 100644
> > --- a/arch/arm64/kernel/entry.S
> > +++ b/arch/arm64/kernel/entry.S
> > @@ -941,6 +941,14 @@ __ni_sys_trace:
> > sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
> > bic \tmp, \tmp, #USER_ASID_FLAG
> > msr ttbr1_el1, \tmp
> > +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
>
> Shouldn't we put this inside an #ifdef QCOM_FALKOR_ERRATUM_1003
> so that we don't even emit nops in case we have the errata
> disabled? Or did I miss something in the alternatives assembly
> code?
Yes, you're right. Thanks!
Will
next prev parent reply other threads:[~2017-11-20 18:05 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-17 18:21 [PATCH 00/18] arm64: Unmap the kernel whilst running in userspace (KAISER) Will Deacon
2017-11-17 18:21 ` [PATCH 01/18] arm64: mm: Use non-global mappings for kernel space Will Deacon
2017-11-17 18:21 ` [PATCH 02/18] arm64: mm: Temporarily disable ARM64_SW_TTBR0_PAN Will Deacon
2017-11-17 18:21 ` [PATCH 03/18] arm64: mm: Move ASID from TTBR0 to TTBR1 Will Deacon
2017-11-17 18:21 ` [PATCH 04/18] arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003 Will Deacon
2017-11-17 18:21 ` [PATCH 05/18] arm64: mm: Rename post_ttbr0_update_workaround Will Deacon
2017-11-17 18:21 ` [PATCH 06/18] arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN Will Deacon
2017-11-17 18:21 ` [PATCH 07/18] arm64: mm: Allocate ASIDs in pairs Will Deacon
2017-11-17 18:21 ` [PATCH 08/18] arm64: mm: Add arm64_kernel_mapped_at_el0 helper using static key Will Deacon
2017-11-17 18:21 ` [PATCH 09/18] arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI Will Deacon
2017-11-17 18:21 ` [PATCH 10/18] arm64: entry: Add exception trampoline page for exceptions from EL0 Will Deacon
2017-11-17 18:21 ` [PATCH 11/18] arm64: mm: Map entry trampoline into trampoline and kernel page tables Will Deacon
2017-11-17 18:21 ` [PATCH 12/18] arm64: entry: Explicitly pass exception level to kernel_ventry macro Will Deacon
2017-11-17 18:21 ` [PATCH 13/18] arm64: entry: Hook up entry trampoline to exception vectors Will Deacon
2017-11-17 18:21 ` [PATCH 14/18] arm64: erratum: Work around Falkor erratum #E1003 in trampoline code Will Deacon
2017-11-18 0:27 ` Stephen Boyd
2017-11-20 18:05 ` Will Deacon [this message]
2017-11-17 18:21 ` [PATCH 15/18] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks Will Deacon
2017-11-17 18:21 ` [PATCH 16/18] arm64: entry: Add fake CPU feature for mapping the kernel at EL0 Will Deacon
2017-11-17 18:22 ` [PATCH 17/18] arm64: makefile: Ensure TEXT_OFFSET doesn't overlap with trampoline Will Deacon
2017-11-17 18:22 ` [PATCH 18/18] arm64: Kconfig: Add CONFIG_UNMAP_KERNEL_AT_EL0 Will Deacon
2017-11-22 16:52 ` Marc Zyngier
2017-11-22 19:36 ` Will Deacon
2017-11-18 0:19 ` [PATCH 00/18] arm64: Unmap the kernel whilst running in userspace (KAISER) Stephen Boyd
2017-11-20 18:03 ` Will Deacon
2017-11-18 15:25 ` Ard Biesheuvel
2017-11-20 18:06 ` Will Deacon
2017-11-20 18:20 ` Ard Biesheuvel
2017-11-22 19:37 ` Will Deacon
2017-11-20 22:50 ` Laura Abbott
2017-11-22 19:37 ` Will Deacon
2017-11-22 16:19 ` Pavel Machek
2017-11-22 19:37 ` Will Deacon
2017-11-22 22:36 ` Pavel Machek
2017-11-22 21:19 ` Ard Biesheuvel
2017-11-22 22:33 ` Pavel Machek
2017-11-22 23:19 ` Ard Biesheuvel
2017-11-22 23:37 ` Pavel Machek
2017-11-23 6:51 ` Ard Biesheuvel
2017-11-23 9:07 ` Pavel Machek
2017-11-23 9:23 ` Ard Biesheuvel
2017-11-23 10:46 ` Pavel Machek
2017-11-23 11:38 ` Ard Biesheuvel
2017-11-23 17:54 ` Pavel Machek
2017-11-23 18:17 ` Ard Biesheuvel
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