From: robh@kernel.org (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/9] dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation
Date: Thu, 30 Nov 2017 20:21:34 -0600 [thread overview]
Message-ID: <20171201022134.ua2a7jc5n44m4qb2@rob-hp-laptop> (raw)
In-Reply-To: <20171129201849.17522-3-f.fainelli@gmail.com>
On Wed, Nov 29, 2017 at 12:18:42PM -0800, Florian Fainelli wrote:
> Correct the Device Tree bindings for the HIF_CPUBIUCTRL node whose
> compatible string is actually brcm,bcm<chip-id>-cpu-biu-ctrl. Also
> document in the binding the fallback property
> ("brcm,brcmstb-cpu-biu-ctrl") and update the example accordingly.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
> index 790e6b0b8306..05be8d1f7be6 100644
> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
> @@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general
> system control is required:
>
> - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
> - - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
> + - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
> + "brcm,brcmstb-cpu-biu-ctrl",
> + "syscon"
> - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
>
> -hif-cpubiuctrl node
> +cpu-biu-ctrl node
> -------------------
> -SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
> -(BIU) block which controls and interfaces the CPU complex to the different
> -Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
> -offers a feature called Write Pairing which consists in collapsing two adjacent
> -cache lines into a single (bursted) write transaction towards the memory
> -controller (MEMC) to maximize write bandwidth.
> +SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
> +specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
> +complex to the different Memory Controller Ports (MCP), one per memory
> +controller (MEMC). This BIU block offers a feature called Write Pairing which
> +consists in collapsing two adjacent cache lines into a single (bursted) write
> +transaction towards the memory controller (MEMC) to maximize write bandwidth.
>
> Required properties:
>
> - - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
> + - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "syscon"
Doesn't this need "brcm,brcmstb-cpu-biu-ctrl" too?
>
> Optional properties:
>
> @@ -52,7 +54,7 @@ example:
> };
>
> hif_cpubiuctrl: syscon at 3e2400 {
> - compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
> + compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
> reg = <0x3e2400 0x5b4>;
> brcm,write-pairing;
> };
> --
> 2.9.3
>
next prev parent reply other threads:[~2017-12-01 2:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-29 20:18 [PATCH 0/9] soc: brcmstb: biuctrl updates for 64-bit chips Florian Fainelli
2017-11-29 20:18 ` [PATCH 1/9] dt-bindings: arm: Add entry for Broadcom Brahma-B53 Florian Fainelli
2017-12-01 2:18 ` Rob Herring
2017-11-29 20:18 ` [PATCH 2/9] dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation Florian Fainelli
2017-12-01 2:21 ` Rob Herring [this message]
2017-11-29 20:18 ` [PATCH 3/9] soc: brcmstb: Make CPU credit offset more parameterized Florian Fainelli
2017-11-29 20:18 ` [PATCH 4/9] soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs Florian Fainelli
2017-11-29 20:18 ` [PATCH 5/9] soc: brcmstb: biuctrl: Prepare for saving/restoring other registers Florian Fainelli
2017-11-29 20:18 ` [PATCH 6/9] soc: brcmstb: biuctrl: Wire-up new registers Florian Fainelli
2017-11-29 20:18 ` [PATCH 7/9] soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings Florian Fainelli
2017-11-29 20:18 ` [PATCH 8/9] soc: brcmstb: Split initialization Florian Fainelli
2017-11-29 20:18 ` [PATCH 9/9] soc: brcmstb: biuctrl: Move to early_initcall Florian Fainelli
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