From mboxrd@z Thu Jan 1 00:00:00 1970 From: yixun.lan@amlogic.com (Yixun Lan) Date: Mon, 4 Dec 2017 14:00:18 +0800 Subject: [PATCH 3/3] ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC In-Reply-To: <20171204060018.8856-1-yixun.lan@amlogic.com> References: <20171204060018.8856-1-yixun.lan@amlogic.com> Message-ID: <20171204060018.8856-4-yixun.lan@amlogic.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Jian Hu Add PWM DT info for the Amlogic's Meson-Axg SoC. Signed-off-by: Jian Hu Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 120 +++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 92f65eec3e18..f7f228701df1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -177,6 +177,24 @@ clock-names = "clk_i2c"; }; + pwm_ab: pwm at 1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_cd: pwm at 1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_A: serial at 24000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; reg = <0x0 0x24000 0x0 0x14>; @@ -368,6 +386,90 @@ function = "i2c3"; }; }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; }; }; @@ -435,6 +537,24 @@ clock-names = "clk_i2c"; }; + pwm_AO_ab: pwm at 7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + + pwm_AO_cd: pwm at 2000 { + compatible = "amlogic,axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, <&xtal>; + clock-names = "clkin0", "clkin1"; + status = "disabled"; + }; + uart_AO: serial at 3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; -- 2.15.0