* [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables. @ 2017-12-06 11:10 ` Enric Balletbo i Serra 2017-12-06 11:10 ` [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3 Enric Balletbo i Serra ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Enric Balletbo i Serra @ 2017-12-06 11:10 UTC (permalink / raw) To: linux-arm-kernel From: Benson Leung <bleung@chromium.org> Extend the driver to notify host and device type cables and the presence of power. Signed-off-by: Benson Leung <bleung@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> --- drivers/extcon/extcon-usbc-cros-ec.c | 142 ++++++++++++++++++++++++++++++++++- include/linux/mfd/cros_ec_commands.h | 17 +++++ 2 files changed, 155 insertions(+), 4 deletions(-) diff --git a/drivers/extcon/extcon-usbc-cros-ec.c b/drivers/extcon/extcon-usbc-cros-ec.c index 6187f73..6721ab0 100644 --- a/drivers/extcon/extcon-usbc-cros-ec.c +++ b/drivers/extcon/extcon-usbc-cros-ec.c @@ -34,16 +34,26 @@ struct cros_ec_extcon_info { struct notifier_block notifier; + unsigned int dr; /* data role */ + bool pr; /* power role (true if VBUS enabled) */ bool dp; /* DisplayPort enabled */ bool mux; /* SuperSpeed (usb3) enabled */ unsigned int power_type; }; static const unsigned int usb_type_c_cable[] = { + EXTCON_USB, + EXTCON_USB_HOST, EXTCON_DISP_DP, EXTCON_NONE, }; +enum usb_data_roles { + DR_NONE, + DR_HOST, + DR_DEVICE, +}; + /** * cros_ec_pd_command() - Send a command to the EC. * @info: pointer to struct cros_ec_extcon_info @@ -150,6 +160,7 @@ static int cros_ec_usb_get_role(struct cros_ec_extcon_info *info, pd_control.port = info->port_id; pd_control.role = USB_PD_CTRL_ROLE_NO_CHANGE; pd_control.mux = USB_PD_CTRL_MUX_NO_CHANGE; + pd_control.swap = USB_PD_CTRL_SWAP_NONE; ret = cros_ec_pd_command(info, EC_CMD_USB_PD_CONTROL, 1, &pd_control, sizeof(pd_control), &resp, sizeof(resp)); @@ -183,11 +194,72 @@ static int cros_ec_pd_get_num_ports(struct cros_ec_extcon_info *info) return resp.num_ports; } +static const char *cros_ec_usb_role_string(unsigned int role) +{ + return role == DR_NONE ? "DISCONNECTED" : + (role == DR_HOST ? "DFP" : "UFP"); +} + +static const char *cros_ec_usb_power_type_string(unsigned int type) +{ + switch (type) { + case USB_CHG_TYPE_NONE: + return "USB_CHG_TYPE_NONE"; + case USB_CHG_TYPE_PD: + return "USB_CHG_TYPE_PD"; + case USB_CHG_TYPE_PROPRIETARY: + return "USB_CHG_TYPE_PROPRIETARY"; + case USB_CHG_TYPE_C: + return "USB_CHG_TYPE_C"; + case USB_CHG_TYPE_BC12_DCP: + return "USB_CHG_TYPE_BC12_DCP"; + case USB_CHG_TYPE_BC12_CDP: + return "USB_CHG_TYPE_BC12_CDP"; + case USB_CHG_TYPE_BC12_SDP: + return "USB_CHG_TYPE_BC12_SDP"; + case USB_CHG_TYPE_OTHER: + return "USB_CHG_TYPE_OTHER"; + case USB_CHG_TYPE_VBUS: + return "USB_CHG_TYPE_VBUS"; + case USB_CHG_TYPE_UNKNOWN: + return "USB_CHG_TYPE_UNKNOWN"; + default: + return "USB_CHG_TYPE_UNKNOWN"; + } +} + +static bool cros_ec_usb_power_type_is_wall_wart(unsigned int type, + unsigned int role) +{ + switch (type) { + /* FIXME : Guppy, Donnettes, and other chargers will be miscategorized + * because they identify with USB_CHG_TYPE_C, but we can't return true + * here from that code because that breaks Suzy-Q and other kinds of + * USB Type-C cables and peripherals. + */ + case USB_CHG_TYPE_PROPRIETARY: + case USB_CHG_TYPE_BC12_DCP: + return true; + case USB_CHG_TYPE_PD: + case USB_CHG_TYPE_C: + case USB_CHG_TYPE_BC12_CDP: + case USB_CHG_TYPE_BC12_SDP: + case USB_CHG_TYPE_OTHER: + case USB_CHG_TYPE_VBUS: + case USB_CHG_TYPE_UNKNOWN: + case USB_CHG_TYPE_NONE: + default: + return false; + } +} + static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, bool force) { struct device *dev = info->dev; int role, power_type; + unsigned int dr = DR_NONE; + bool pr = false; bool polarity = false; bool dp = false; bool mux = false; @@ -206,9 +278,12 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, dev_err(dev, "failed getting role err = %d\n", role); return role; } + dev_dbg(dev, "disconnected\n"); } else { int pd_mux_state; + dr = (role & PD_CTRL_RESP_ROLE_DATA) ? DR_HOST : DR_DEVICE; + pr = (role & PD_CTRL_RESP_ROLE_POWER); pd_mux_state = cros_ec_usb_get_pd_mux_state(info); if (pd_mux_state < 0) pd_mux_state = USB_PD_MUX_USB_ENABLED; @@ -216,20 +291,62 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, dp = pd_mux_state & USB_PD_MUX_DP_ENABLED; mux = pd_mux_state & USB_PD_MUX_USB_ENABLED; hpd = pd_mux_state & USB_PD_MUX_HPD_IRQ; - } - if (force || info->dp != dp || info->mux != mux || - info->power_type != power_type) { + dev_dbg(dev, + "connected role 0x%x pwr type %d dr %d pr %d pol %d mux %d dp %d hpd %d\n", + role, power_type, dr, pr, polarity, mux, dp, hpd); + } + /* + * When there is no USB host (e.g. USB PD charger), + * we are not really a UFP for the AP. + */ + if (dr == DR_DEVICE && + cros_ec_usb_power_type_is_wall_wart(power_type, role)) + dr = DR_NONE; + + if (force || info->dr != dr || info->pr != pr || info->dp != dp || + info->mux != mux || info->power_type != power_type) { + bool host_connected = false, device_connected = false; + + dev_dbg(dev, "Type/Role switch! type = %s role = %s\n", + cros_ec_usb_power_type_string(power_type), + cros_ec_usb_role_string(dr)); + info->dr = dr; + info->pr = pr; info->dp = dp; info->mux = mux; info->power_type = power_type; - extcon_set_state(info->edev, EXTCON_DISP_DP, dp); + if (dr == DR_DEVICE) + device_connected = true; + else if (dr == DR_HOST) + host_connected = true; + extcon_set_state(info->edev, EXTCON_USB, device_connected); + extcon_set_state(info->edev, EXTCON_USB_HOST, host_connected); + extcon_set_state(info->edev, EXTCON_DISP_DP, dp); + extcon_set_property(info->edev, EXTCON_USB, + EXTCON_PROP_USB_VBUS, + (union extcon_property_value)(int)pr); + extcon_set_property(info->edev, EXTCON_USB_HOST, + EXTCON_PROP_USB_VBUS, + (union extcon_property_value)(int)pr); + extcon_set_property(info->edev, EXTCON_USB, + EXTCON_PROP_USB_TYPEC_POLARITY, + (union extcon_property_value)(int)polarity); + extcon_set_property(info->edev, EXTCON_USB_HOST, + EXTCON_PROP_USB_TYPEC_POLARITY, + (union extcon_property_value)(int)polarity); extcon_set_property(info->edev, EXTCON_DISP_DP, EXTCON_PROP_USB_TYPEC_POLARITY, (union extcon_property_value)(int)polarity); + extcon_set_property(info->edev, EXTCON_USB, + EXTCON_PROP_USB_SS, + (union extcon_property_value)(int)mux); + extcon_set_property(info->edev, EXTCON_USB_HOST, + EXTCON_PROP_USB_SS, + (union extcon_property_value)(int)mux); extcon_set_property(info->edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS, (union extcon_property_value)(int)mux); @@ -237,6 +354,8 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, EXTCON_PROP_DISP_HPD, (union extcon_property_value)(int)hpd); + extcon_sync(info->edev, EXTCON_USB); + extcon_sync(info->edev, EXTCON_USB_HOST); extcon_sync(info->edev, EXTCON_DISP_DP); } else if (hpd) { @@ -322,13 +441,28 @@ static int extcon_cros_ec_probe(struct platform_device *pdev) return ret; } + extcon_set_property_capability(info->edev, EXTCON_USB, + EXTCON_PROP_USB_VBUS); + extcon_set_property_capability(info->edev, EXTCON_USB_HOST, + EXTCON_PROP_USB_VBUS); + extcon_set_property_capability(info->edev, EXTCON_USB, + EXTCON_PROP_USB_TYPEC_POLARITY); + extcon_set_property_capability(info->edev, EXTCON_USB_HOST, + EXTCON_PROP_USB_TYPEC_POLARITY); extcon_set_property_capability(info->edev, EXTCON_DISP_DP, EXTCON_PROP_USB_TYPEC_POLARITY); + extcon_set_property_capability(info->edev, EXTCON_USB, + EXTCON_PROP_USB_SS); + extcon_set_property_capability(info->edev, EXTCON_USB_HOST, + EXTCON_PROP_USB_SS); extcon_set_property_capability(info->edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS); extcon_set_property_capability(info->edev, EXTCON_DISP_DP, EXTCON_PROP_DISP_HPD); + info->dr = DR_NONE; + info->pr = false; + platform_set_drvdata(pdev, info); /* Get PD events from the EC */ diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h index 2b16e95..c907353 100644 --- a/include/linux/mfd/cros_ec_commands.h +++ b/include/linux/mfd/cros_ec_commands.h @@ -2904,16 +2904,33 @@ enum usb_pd_control_mux { USB_PD_CTRL_MUX_AUTO = 5, }; +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT +}; + struct ec_params_usb_pd_control { uint8_t port; uint8_t role; uint8_t mux; + uint8_t swap; } __packed; #define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ #define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ #define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ +#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ + struct ec_response_usb_pd_control_v1 { uint8_t enabled; uint8_t role; -- 2.9.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3. 2017-12-06 11:10 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Enric Balletbo i Serra @ 2017-12-06 11:10 ` Enric Balletbo i Serra 2017-12-06 11:20 ` Heiko Stübner 2017-12-06 11:10 ` [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy Enric Balletbo i Serra ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Enric Balletbo i Serra @ 2017-12-06 11:10 UTC (permalink / raw) To: linux-arm-kernel This patch adds the usb3-phy for both of the two dwc3 controllers on rk3399. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 17e5e1a..c18ff88 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -397,9 +397,11 @@ #size-cells = <2>; ranges; clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; status = "disabled"; usbdrd_dwc3_0: dwc3 { @@ -407,14 +409,15 @@ reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; dr_mode = "otg"; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; status = "disabled"; }; }; @@ -425,9 +428,11 @@ #size-cells = <2>; ranges; clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; status = "disabled"; usbdrd_dwc3_1: dwc3 { @@ -435,14 +440,15 @@ reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; dr_mode = "otg"; - phys = <&u2phy1_otg>; - phy-names = "usb2-phy"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; status = "disabled"; }; }; @@ -991,6 +997,12 @@ clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; + pd_usb3 at RK3399_PD_USB3 { + reg = <RK3399_PD_USB3>; + clocks = <&cru ACLK_USB3>; + pm_qos = <&qos_usb_otg0>, + <&qos_usb_otg1>; + }; pd_vio at RK3399_PD_VIO { reg = <RK3399_PD_VIO>; #address-cells = <1>; -- 2.9.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3. 2017-12-06 11:10 ` [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3 Enric Balletbo i Serra @ 2017-12-06 11:20 ` Heiko Stübner 2017-12-06 11:27 ` Enric Balletbo i Serra 0 siblings, 1 reply; 9+ messages in thread From: Heiko Stübner @ 2017-12-06 11:20 UTC (permalink / raw) To: linux-arm-kernel Am Mittwoch, 6. Dezember 2017, 12:10:07 CET schrieb Enric Balletbo i Serra: > This patch adds the usb3-phy for both of the two dwc3 controllers on > rk3399. This patch adds quite a bit more than the phy phandles though. The powerdomain addition should definitly be a separate patch and the usb3-grf clock as well. Heiko > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 17e5e1a..c18ff88 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -397,9 +397,11 @@ > #size-cells = <2>; > ranges; > clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, > - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; > + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, > + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; > clock-names = "ref_clk", "suspend_clk", > - "bus_clk", "grf_clk"; > + "bus_clk", "aclk_usb3_rksoc_axi_perf", > + "aclk_usb3", "grf_clk"; > status = "disabled"; > > usbdrd_dwc3_0: dwc3 { > @@ -407,14 +409,15 @@ > reg = <0x0 0xfe800000 0x0 0x100000>; > interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; > dr_mode = "otg"; > - phys = <&u2phy0_otg>; > - phy-names = "usb2-phy"; > + phys = <&u2phy0_otg>, <&tcphy0_usb3>; > + phy-names = "usb2-phy", "usb3-phy"; > phy_type = "utmi_wide"; > snps,dis_enblslpm_quirk; > snps,dis-u2-freeclk-exists-quirk; > snps,dis_u2_susphy_quirk; > snps,dis-del-phy-power-chg-quirk; > snps,dis-tx-ipgap-linecheck-quirk; > + power-domains = <&power RK3399_PD_USB3>; > status = "disabled"; > }; > }; > @@ -425,9 +428,11 @@ > #size-cells = <2>; > ranges; > clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, > - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; > + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, > + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; > clock-names = "ref_clk", "suspend_clk", > - "bus_clk", "grf_clk"; > + "bus_clk", "aclk_usb3_rksoc_axi_perf", > + "aclk_usb3", "grf_clk"; > status = "disabled"; > > usbdrd_dwc3_1: dwc3 { > @@ -435,14 +440,15 @@ > reg = <0x0 0xfe900000 0x0 0x100000>; > interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; > dr_mode = "otg"; > - phys = <&u2phy1_otg>; > - phy-names = "usb2-phy"; > + phys = <&u2phy1_otg>, <&tcphy1_usb3>; > + phy-names = "usb2-phy", "usb3-phy"; > phy_type = "utmi_wide"; > snps,dis_enblslpm_quirk; > snps,dis-u2-freeclk-exists-quirk; > snps,dis_u2_susphy_quirk; > snps,dis-del-phy-power-chg-quirk; > snps,dis-tx-ipgap-linecheck-quirk; > + power-domains = <&power RK3399_PD_USB3>; > status = "disabled"; > }; > }; > @@ -991,6 +997,12 @@ > clocks = <&cru HCLK_SDIO>; > pm_qos = <&qos_sdioaudio>; > }; > + pd_usb3 at RK3399_PD_USB3 { > + reg = <RK3399_PD_USB3>; > + clocks = <&cru ACLK_USB3>; > + pm_qos = <&qos_usb_otg0>, > + <&qos_usb_otg1>; > + }; > pd_vio at RK3399_PD_VIO { > reg = <RK3399_PD_VIO>; > #address-cells = <1>; ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3. 2017-12-06 11:20 ` Heiko Stübner @ 2017-12-06 11:27 ` Enric Balletbo i Serra 0 siblings, 0 replies; 9+ messages in thread From: Enric Balletbo i Serra @ 2017-12-06 11:27 UTC (permalink / raw) To: linux-arm-kernel Hi Heiko, On 06/12/17 12:20, Heiko St?bner wrote: > Am Mittwoch, 6. Dezember 2017, 12:10:07 CET schrieb Enric Balletbo i Serra: >> This patch adds the usb3-phy for both of the two dwc3 controllers on >> rk3399. > > This patch adds quite a bit more than the phy phandles though. > > The powerdomain addition should definitly be a separate patch > and the usb3-grf clock as well. > Ok, I'll split these parts and send in a separate patch in v2. Thanks for the feedback. Enric > > Heiko > > >> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> >> --- >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++-------- >> 1 file changed, 20 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 17e5e1a..c18ff88 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> @@ -397,9 +397,11 @@ >> #size-cells = <2>; >> ranges; >> clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, >> - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; >> + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, >> + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; >> clock-names = "ref_clk", "suspend_clk", >> - "bus_clk", "grf_clk"; >> + "bus_clk", "aclk_usb3_rksoc_axi_perf", >> + "aclk_usb3", "grf_clk"; >> status = "disabled"; >> >> usbdrd_dwc3_0: dwc3 { >> @@ -407,14 +409,15 @@ >> reg = <0x0 0xfe800000 0x0 0x100000>; >> interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; >> dr_mode = "otg"; >> - phys = <&u2phy0_otg>; >> - phy-names = "usb2-phy"; >> + phys = <&u2phy0_otg>, <&tcphy0_usb3>; >> + phy-names = "usb2-phy", "usb3-phy"; >> phy_type = "utmi_wide"; >> snps,dis_enblslpm_quirk; >> snps,dis-u2-freeclk-exists-quirk; >> snps,dis_u2_susphy_quirk; >> snps,dis-del-phy-power-chg-quirk; >> snps,dis-tx-ipgap-linecheck-quirk; >> + power-domains = <&power RK3399_PD_USB3>; >> status = "disabled"; >> }; >> }; >> @@ -425,9 +428,11 @@ >> #size-cells = <2>; >> ranges; >> clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, >> - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; >> + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, >> + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; >> clock-names = "ref_clk", "suspend_clk", >> - "bus_clk", "grf_clk"; >> + "bus_clk", "aclk_usb3_rksoc_axi_perf", >> + "aclk_usb3", "grf_clk"; >> status = "disabled"; >> >> usbdrd_dwc3_1: dwc3 { >> @@ -435,14 +440,15 @@ >> reg = <0x0 0xfe900000 0x0 0x100000>; >> interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; >> dr_mode = "otg"; >> - phys = <&u2phy1_otg>; >> - phy-names = "usb2-phy"; >> + phys = <&u2phy1_otg>, <&tcphy1_usb3>; >> + phy-names = "usb2-phy", "usb3-phy"; >> phy_type = "utmi_wide"; >> snps,dis_enblslpm_quirk; >> snps,dis-u2-freeclk-exists-quirk; >> snps,dis_u2_susphy_quirk; >> snps,dis-del-phy-power-chg-quirk; >> snps,dis-tx-ipgap-linecheck-quirk; >> + power-domains = <&power RK3399_PD_USB3>; >> status = "disabled"; >> }; >> }; >> @@ -991,6 +997,12 @@ >> clocks = <&cru HCLK_SDIO>; >> pm_qos = <&qos_sdioaudio>; >> }; >> + pd_usb3 at RK3399_PD_USB3 { >> + reg = <RK3399_PD_USB3>; >> + clocks = <&cru ACLK_USB3>; >> + pm_qos = <&qos_usb_otg0>, >> + <&qos_usb_otg1>; >> + }; >> pd_vio at RK3399_PD_VIO { >> reg = <RK3399_PD_VIO>; >> #address-cells = <1>; > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy. 2017-12-06 11:10 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Enric Balletbo i Serra 2017-12-06 11:10 ` [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3 Enric Balletbo i Serra @ 2017-12-06 11:10 ` Enric Balletbo i Serra 2017-12-06 17:29 ` Brian Norris 2017-12-06 15:43 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Lee Jones 2017-12-07 2:12 ` Chanwoo Choi 3 siblings, 1 reply; 9+ messages in thread From: Enric Balletbo i Serra @ 2017-12-06 11:10 UTC (permalink / raw) To: linux-arm-kernel Enable tcphy and create the cros-ec's extcon node for the USB Type-C port. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 470105d..03f1950 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; + + usbc_extcon0: extcon at 0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + + #extcon-cells = <0>; + }; + + usbc_extcon1: extcon at 1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + + #extcon-cells = <0>; + }; }; }; @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 { rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ }; +&tcphy0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + &u2phy0 { status = "okay"; }; @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 { &usbdrd3_0 { status = "okay"; + extcon = <&usbc_extcon0>; }; &usbdrd_dwc3_0 { @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 { &usbdrd3_1 { status = "okay"; + extcon = <&usbc_extcon1>; }; &usbdrd_dwc3_1 { -- 2.9.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy. 2017-12-06 11:10 ` [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy Enric Balletbo i Serra @ 2017-12-06 17:29 ` Brian Norris 2017-12-13 10:28 ` Enric Balletbo Serra 0 siblings, 1 reply; 9+ messages in thread From: Brian Norris @ 2017-12-06 17:29 UTC (permalink / raw) To: linux-arm-kernel + Alex, Jeffy, Frank Wang Hi, On Wed, Dec 06, 2017 at 12:10:08PM +0100, Enric Balletbo i Serra wrote: > Enable tcphy and create the cros-ec's extcon node for the USB Type-C port. > > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi > index 470105d..03f1950 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi > @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 { > compatible = "google,cros-ec-pwm"; > #pwm-cells = <1>; > }; > + > + usbc_extcon0: extcon at 0 { > + compatible = "google,extcon-usbc-cros-ec"; > + google,usb-port-id = <0>; > + > + #extcon-cells = <0>; > + }; > + > + usbc_extcon1: extcon at 1 { > + compatible = "google,extcon-usbc-cros-ec"; > + google,usb-port-id = <1>; > + > + #extcon-cells = <0>; > + }; > }; > }; > > @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 { > rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ > }; > > +&tcphy0 { > + status = "okay"; > + extcon = <&usbc_extcon0>; > +}; > + > +&tcphy1 { > + status = "okay"; > + extcon = <&usbc_extcon1>; > +}; > + > &u2phy0 { > status = "okay"; > }; > @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 { > > &usbdrd3_0 { > status = "okay"; > + extcon = <&usbc_extcon0>; > }; > > &usbdrd_dwc3_0 { > @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 { > > &usbdrd3_1 { > status = "okay"; > + extcon = <&usbc_extcon1>; > }; > > &usbdrd_dwc3_1 { Seems OK. Also, IIUC, I think if we ever want to support dual-role/OTG, we need an extcon reference in the USB2/OTG PHY that serves these ports too. i.e., u2phy0 and u2phy1? Notably, the PHY driver supports the extcon properties, but it's not documented in Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt yet (we should probably get that fixed). So, anyway, maybe the above isn't a blocker for this patch. Just noticed it while reading. Assuming the driver stuff falls into place: Reviewed-by: Brian Norris <briannorris@chromium.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy. 2017-12-06 17:29 ` Brian Norris @ 2017-12-13 10:28 ` Enric Balletbo Serra 0 siblings, 0 replies; 9+ messages in thread From: Enric Balletbo Serra @ 2017-12-13 10:28 UTC (permalink / raw) To: linux-arm-kernel Hi Brian, 2017-12-06 18:29 GMT+01:00 Brian Norris <briannorris@chromium.org>: > + Alex, Jeffy, Frank Wang > > Hi, > > On Wed, Dec 06, 2017 at 12:10:08PM +0100, Enric Balletbo i Serra wrote: >> Enable tcphy and create the cros-ec's extcon node for the USB Type-C port. >> >> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> >> --- >> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi >> index 470105d..03f1950 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi >> @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 { >> compatible = "google,cros-ec-pwm"; >> #pwm-cells = <1>; >> }; >> + >> + usbc_extcon0: extcon at 0 { >> + compatible = "google,extcon-usbc-cros-ec"; >> + google,usb-port-id = <0>; >> + >> + #extcon-cells = <0>; >> + }; >> + >> + usbc_extcon1: extcon at 1 { >> + compatible = "google,extcon-usbc-cros-ec"; >> + google,usb-port-id = <1>; >> + >> + #extcon-cells = <0>; >> + }; >> }; >> }; >> >> @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 { >> rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ >> }; >> >> +&tcphy0 { >> + status = "okay"; >> + extcon = <&usbc_extcon0>; >> +}; >> + >> +&tcphy1 { >> + status = "okay"; >> + extcon = <&usbc_extcon1>; >> +}; >> + >> &u2phy0 { >> status = "okay"; >> }; >> @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 { >> >> &usbdrd3_0 { >> status = "okay"; >> + extcon = <&usbc_extcon0>; >> }; >> >> &usbdrd_dwc3_0 { >> @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 { >> >> &usbdrd3_1 { >> status = "okay"; >> + extcon = <&usbc_extcon1>; >> }; >> >> &usbdrd_dwc3_1 { > > Seems OK. > > Also, IIUC, I think if we ever want to support dual-role/OTG, we need an > extcon reference in the USB2/OTG PHY that serves these ports too. i.e., > u2phy0 and u2phy1? Notably, the PHY driver supports the extcon > properties, but it's not documented in > Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt yet (we > should probably get that fixed). > I'll take a look at this and send a separate patchset. Thanks. Enric > So, anyway, maybe the above isn't a blocker for this patch. Just noticed > it while reading. Assuming the driver stuff falls into place: > > Reviewed-by: Brian Norris <briannorris@chromium.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables. 2017-12-06 11:10 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Enric Balletbo i Serra 2017-12-06 11:10 ` [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3 Enric Balletbo i Serra 2017-12-06 11:10 ` [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy Enric Balletbo i Serra @ 2017-12-06 15:43 ` Lee Jones 2017-12-07 2:12 ` Chanwoo Choi 3 siblings, 0 replies; 9+ messages in thread From: Lee Jones @ 2017-12-06 15:43 UTC (permalink / raw) To: linux-arm-kernel On Wed, 06 Dec 2017, Enric Balletbo i Serra wrote: > From: Benson Leung <bleung@chromium.org> > > Extend the driver to notify host and device type cables and the presence > of power. > > Signed-off-by: Benson Leung <bleung@chromium.org> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > drivers/extcon/extcon-usbc-cros-ec.c | 142 ++++++++++++++++++++++++++++++++++- > include/linux/mfd/cros_ec_commands.h | 17 +++++ > 2 files changed, 155 insertions(+), 4 deletions(-) [...] > diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h > index 2b16e95..c907353 100644 > --- a/include/linux/mfd/cros_ec_commands.h > +++ b/include/linux/mfd/cros_ec_commands.h > @@ -2904,16 +2904,33 @@ enum usb_pd_control_mux { > USB_PD_CTRL_MUX_AUTO = 5, > }; > > +enum usb_pd_control_swap { > + USB_PD_CTRL_SWAP_NONE = 0, > + USB_PD_CTRL_SWAP_DATA = 1, > + USB_PD_CTRL_SWAP_POWER = 2, > + USB_PD_CTRL_SWAP_VCONN = 3, > + USB_PD_CTRL_SWAP_COUNT > +}; > + > struct ec_params_usb_pd_control { > uint8_t port; > uint8_t role; > uint8_t mux; > + uint8_t swap; > } __packed; > > #define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ > #define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ > #define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ > > +#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ > +#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ > +#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ > +#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ > +#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ > +#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ > +#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ Looks like the BIT() macro would serve you well here. -- Lee Jones Linaro Services Technical Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables. 2017-12-06 11:10 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Enric Balletbo i Serra ` (2 preceding siblings ...) 2017-12-06 15:43 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Lee Jones @ 2017-12-07 2:12 ` Chanwoo Choi 3 siblings, 0 replies; 9+ messages in thread From: Chanwoo Choi @ 2017-12-07 2:12 UTC (permalink / raw) To: linux-arm-kernel Hi Enric, On 2017? 12? 06? 20:10, Enric Balletbo i Serra wrote: > From: Benson Leung <bleung@chromium.org> > > Extend the driver to notify host and device type cables and the presence > of power. > > Signed-off-by: Benson Leung <bleung@chromium.org> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > drivers/extcon/extcon-usbc-cros-ec.c | 142 ++++++++++++++++++++++++++++++++++- > include/linux/mfd/cros_ec_commands.h | 17 +++++ > 2 files changed, 155 insertions(+), 4 deletions(-) Looks good to me. After you uses the BIT() macro as the Lee's comment on v2, I'll merge this patch. Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> > > diff --git a/drivers/extcon/extcon-usbc-cros-ec.c b/drivers/extcon/extcon-usbc-cros-ec.c > index 6187f73..6721ab0 100644 > --- a/drivers/extcon/extcon-usbc-cros-ec.c > +++ b/drivers/extcon/extcon-usbc-cros-ec.c > @@ -34,16 +34,26 @@ struct cros_ec_extcon_info { > > struct notifier_block notifier; > > + unsigned int dr; /* data role */ > + bool pr; /* power role (true if VBUS enabled) */ > bool dp; /* DisplayPort enabled */ > bool mux; /* SuperSpeed (usb3) enabled */ > unsigned int power_type; > }; > > static const unsigned int usb_type_c_cable[] = { > + EXTCON_USB, > + EXTCON_USB_HOST, > EXTCON_DISP_DP, > EXTCON_NONE, > }; > > +enum usb_data_roles { > + DR_NONE, > + DR_HOST, > + DR_DEVICE, > +}; > + > /** > * cros_ec_pd_command() - Send a command to the EC. > * @info: pointer to struct cros_ec_extcon_info > @@ -150,6 +160,7 @@ static int cros_ec_usb_get_role(struct cros_ec_extcon_info *info, > pd_control.port = info->port_id; > pd_control.role = USB_PD_CTRL_ROLE_NO_CHANGE; > pd_control.mux = USB_PD_CTRL_MUX_NO_CHANGE; > + pd_control.swap = USB_PD_CTRL_SWAP_NONE; > ret = cros_ec_pd_command(info, EC_CMD_USB_PD_CONTROL, 1, > &pd_control, sizeof(pd_control), > &resp, sizeof(resp)); > @@ -183,11 +194,72 @@ static int cros_ec_pd_get_num_ports(struct cros_ec_extcon_info *info) > return resp.num_ports; > } > > +static const char *cros_ec_usb_role_string(unsigned int role) > +{ > + return role == DR_NONE ? "DISCONNECTED" : > + (role == DR_HOST ? "DFP" : "UFP"); > +} > + > +static const char *cros_ec_usb_power_type_string(unsigned int type) > +{ > + switch (type) { > + case USB_CHG_TYPE_NONE: > + return "USB_CHG_TYPE_NONE"; > + case USB_CHG_TYPE_PD: > + return "USB_CHG_TYPE_PD"; > + case USB_CHG_TYPE_PROPRIETARY: > + return "USB_CHG_TYPE_PROPRIETARY"; > + case USB_CHG_TYPE_C: > + return "USB_CHG_TYPE_C"; > + case USB_CHG_TYPE_BC12_DCP: > + return "USB_CHG_TYPE_BC12_DCP"; > + case USB_CHG_TYPE_BC12_CDP: > + return "USB_CHG_TYPE_BC12_CDP"; > + case USB_CHG_TYPE_BC12_SDP: > + return "USB_CHG_TYPE_BC12_SDP"; > + case USB_CHG_TYPE_OTHER: > + return "USB_CHG_TYPE_OTHER"; > + case USB_CHG_TYPE_VBUS: > + return "USB_CHG_TYPE_VBUS"; > + case USB_CHG_TYPE_UNKNOWN: > + return "USB_CHG_TYPE_UNKNOWN"; > + default: > + return "USB_CHG_TYPE_UNKNOWN"; > + } > +} > + > +static bool cros_ec_usb_power_type_is_wall_wart(unsigned int type, > + unsigned int role) > +{ > + switch (type) { > + /* FIXME : Guppy, Donnettes, and other chargers will be miscategorized > + * because they identify with USB_CHG_TYPE_C, but we can't return true > + * here from that code because that breaks Suzy-Q and other kinds of > + * USB Type-C cables and peripherals. > + */ > + case USB_CHG_TYPE_PROPRIETARY: > + case USB_CHG_TYPE_BC12_DCP: > + return true; > + case USB_CHG_TYPE_PD: > + case USB_CHG_TYPE_C: > + case USB_CHG_TYPE_BC12_CDP: > + case USB_CHG_TYPE_BC12_SDP: > + case USB_CHG_TYPE_OTHER: > + case USB_CHG_TYPE_VBUS: > + case USB_CHG_TYPE_UNKNOWN: > + case USB_CHG_TYPE_NONE: > + default: > + return false; > + } > +} > + > static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, > bool force) > { > struct device *dev = info->dev; > int role, power_type; > + unsigned int dr = DR_NONE; > + bool pr = false; > bool polarity = false; > bool dp = false; > bool mux = false; > @@ -206,9 +278,12 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, > dev_err(dev, "failed getting role err = %d\n", role); > return role; > } > + dev_dbg(dev, "disconnected\n"); > } else { > int pd_mux_state; > > + dr = (role & PD_CTRL_RESP_ROLE_DATA) ? DR_HOST : DR_DEVICE; > + pr = (role & PD_CTRL_RESP_ROLE_POWER); > pd_mux_state = cros_ec_usb_get_pd_mux_state(info); > if (pd_mux_state < 0) > pd_mux_state = USB_PD_MUX_USB_ENABLED; > @@ -216,20 +291,62 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, > dp = pd_mux_state & USB_PD_MUX_DP_ENABLED; > mux = pd_mux_state & USB_PD_MUX_USB_ENABLED; > hpd = pd_mux_state & USB_PD_MUX_HPD_IRQ; > - } > > - if (force || info->dp != dp || info->mux != mux || > - info->power_type != power_type) { > + dev_dbg(dev, > + "connected role 0x%x pwr type %d dr %d pr %d pol %d mux %d dp %d hpd %d\n", > + role, power_type, dr, pr, polarity, mux, dp, hpd); > + } > > + /* > + * When there is no USB host (e.g. USB PD charger), > + * we are not really a UFP for the AP. > + */ > + if (dr == DR_DEVICE && > + cros_ec_usb_power_type_is_wall_wart(power_type, role)) > + dr = DR_NONE; > + > + if (force || info->dr != dr || info->pr != pr || info->dp != dp || > + info->mux != mux || info->power_type != power_type) { > + bool host_connected = false, device_connected = false; > + > + dev_dbg(dev, "Type/Role switch! type = %s role = %s\n", > + cros_ec_usb_power_type_string(power_type), > + cros_ec_usb_role_string(dr)); > + info->dr = dr; > + info->pr = pr; > info->dp = dp; > info->mux = mux; > info->power_type = power_type; > > - extcon_set_state(info->edev, EXTCON_DISP_DP, dp); > + if (dr == DR_DEVICE) > + device_connected = true; > + else if (dr == DR_HOST) > + host_connected = true; > > + extcon_set_state(info->edev, EXTCON_USB, device_connected); > + extcon_set_state(info->edev, EXTCON_USB_HOST, host_connected); > + extcon_set_state(info->edev, EXTCON_DISP_DP, dp); > + extcon_set_property(info->edev, EXTCON_USB, > + EXTCON_PROP_USB_VBUS, > + (union extcon_property_value)(int)pr); > + extcon_set_property(info->edev, EXTCON_USB_HOST, > + EXTCON_PROP_USB_VBUS, > + (union extcon_property_value)(int)pr); > + extcon_set_property(info->edev, EXTCON_USB, > + EXTCON_PROP_USB_TYPEC_POLARITY, > + (union extcon_property_value)(int)polarity); > + extcon_set_property(info->edev, EXTCON_USB_HOST, > + EXTCON_PROP_USB_TYPEC_POLARITY, > + (union extcon_property_value)(int)polarity); > extcon_set_property(info->edev, EXTCON_DISP_DP, > EXTCON_PROP_USB_TYPEC_POLARITY, > (union extcon_property_value)(int)polarity); > + extcon_set_property(info->edev, EXTCON_USB, > + EXTCON_PROP_USB_SS, > + (union extcon_property_value)(int)mux); > + extcon_set_property(info->edev, EXTCON_USB_HOST, > + EXTCON_PROP_USB_SS, > + (union extcon_property_value)(int)mux); > extcon_set_property(info->edev, EXTCON_DISP_DP, > EXTCON_PROP_USB_SS, > (union extcon_property_value)(int)mux); > @@ -237,6 +354,8 @@ static int extcon_cros_ec_detect_cable(struct cros_ec_extcon_info *info, > EXTCON_PROP_DISP_HPD, > (union extcon_property_value)(int)hpd); > > + extcon_sync(info->edev, EXTCON_USB); > + extcon_sync(info->edev, EXTCON_USB_HOST); > extcon_sync(info->edev, EXTCON_DISP_DP); > > } else if (hpd) { > @@ -322,13 +441,28 @@ static int extcon_cros_ec_probe(struct platform_device *pdev) > return ret; > } > > + extcon_set_property_capability(info->edev, EXTCON_USB, > + EXTCON_PROP_USB_VBUS); > + extcon_set_property_capability(info->edev, EXTCON_USB_HOST, > + EXTCON_PROP_USB_VBUS); > + extcon_set_property_capability(info->edev, EXTCON_USB, > + EXTCON_PROP_USB_TYPEC_POLARITY); > + extcon_set_property_capability(info->edev, EXTCON_USB_HOST, > + EXTCON_PROP_USB_TYPEC_POLARITY); > extcon_set_property_capability(info->edev, EXTCON_DISP_DP, > EXTCON_PROP_USB_TYPEC_POLARITY); > + extcon_set_property_capability(info->edev, EXTCON_USB, > + EXTCON_PROP_USB_SS); > + extcon_set_property_capability(info->edev, EXTCON_USB_HOST, > + EXTCON_PROP_USB_SS); > extcon_set_property_capability(info->edev, EXTCON_DISP_DP, > EXTCON_PROP_USB_SS); > extcon_set_property_capability(info->edev, EXTCON_DISP_DP, > EXTCON_PROP_DISP_HPD); > > + info->dr = DR_NONE; > + info->pr = false; > + > platform_set_drvdata(pdev, info); > > /* Get PD events from the EC */ > diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h > index 2b16e95..c907353 100644 > --- a/include/linux/mfd/cros_ec_commands.h > +++ b/include/linux/mfd/cros_ec_commands.h > @@ -2904,16 +2904,33 @@ enum usb_pd_control_mux { > USB_PD_CTRL_MUX_AUTO = 5, > }; > > +enum usb_pd_control_swap { > + USB_PD_CTRL_SWAP_NONE = 0, > + USB_PD_CTRL_SWAP_DATA = 1, > + USB_PD_CTRL_SWAP_POWER = 2, > + USB_PD_CTRL_SWAP_VCONN = 3, > + USB_PD_CTRL_SWAP_COUNT > +}; > + > struct ec_params_usb_pd_control { > uint8_t port; > uint8_t role; > uint8_t mux; > + uint8_t swap; > } __packed; > > #define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ > #define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ > #define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ > > +#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ > +#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ > +#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ > +#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ > +#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ > +#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ > +#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ > + > struct ec_response_usb_pd_control_v1 { > uint8_t enabled; > uint8_t role; > -- Best Regards, Chanwoo Choi Samsung Electronics ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-12-13 10:28 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2017-12-06 11:10 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Enric Balletbo i Serra
2017-12-06 11:10 ` [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3 Enric Balletbo i Serra
2017-12-06 11:20 ` Heiko Stübner
2017-12-06 11:27 ` Enric Balletbo i Serra
2017-12-06 11:10 ` [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy Enric Balletbo i Serra
2017-12-06 17:29 ` Brian Norris
2017-12-13 10:28 ` Enric Balletbo Serra
2017-12-06 15:43 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Lee Jones
2017-12-07 2:12 ` Chanwoo Choi
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