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From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 4/5] clk: aspeed: Register gated clocks
Date: Thu, 21 Dec 2017 15:39:27 -0800	[thread overview]
Message-ID: <20171221233927.GE7997@codeaurora.org> (raw)
In-Reply-To: <20171128071908.12279-5-joel@jms.id.au>

On 11/28, Joel Stanley wrote:
> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
> index 839243691b26..b5dc3e298693 100644
> --- a/drivers/clk/clk-aspeed.c
> +++ b/drivers/clk/clk-aspeed.c
> @@ -202,6 +202,107 @@ static const struct aspeed_clk_soc_data ast2400_data = {
>  	.calc_pll = aspeed_ast2400_calc_pll,
>  };
>  
> +static int aspeed_clk_enable(struct clk_hw *hw)
> +{
> +	struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
> +	unsigned long flags;
> +	u32 clk = BIT(gate->clock_idx);
> +	u32 rst = BIT(gate->reset_idx);
> +
> +	spin_lock_irqsave(gate->lock, flags);
> +
> +	if (gate->reset_idx >= 0) {
> +		/* Put IP in reset */
> +		regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
> +
> +		/* Delay 100us */
> +		udelay(100);
> +	}
> +
> +	/* Enable clock */
> +	regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0);
> +
> +	if (gate->reset_idx >= 0) {
> +		/* Delay 10ms */
> +		/* TODO: can we sleep here? */
> +		msleep(10);

No you can't sleep here. It needs to delay because this is inside
spinlock_irqsave.

> +
> +		/* Take IP out of reset */
> +		regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
> +	}
> +
> +	spin_unlock_irqrestore(gate->lock, flags);
> +
> +	return 0;
> +}

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2017-12-21 23:39 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-28  7:19 [PATCH v6 0/5] clk: Add Aspeed clock driver Joel Stanley
2017-11-28  7:19 ` [PATCH v6 1/5] clk: Add clock driver for ASPEED BMC SoCs Joel Stanley
2017-12-20  3:42   ` Joel Stanley
2017-11-28  7:19 ` [PATCH v6 2/5] clk: aspeed: Register core clocks Joel Stanley
2017-11-28  7:19 ` [PATCH v6 3/5] clk: aspeed: Add platform driver and register PLLs Joel Stanley
2017-11-28  7:19 ` [PATCH v6 4/5] clk: aspeed: Register gated clocks Joel Stanley
2017-12-21 23:39   ` Stephen Boyd [this message]
2017-12-22  2:36     ` Benjamin Herrenschmidt
2017-12-22  2:43       ` Benjamin Herrenschmidt
2017-12-27  1:32         ` Stephen Boyd
2017-12-29 22:03           ` Benjamin Herrenschmidt
2018-01-02  5:46             ` Benjamin Herrenschmidt
2018-01-02 18:16             ` Stephen Boyd
2017-11-28  7:19 ` [PATCH v6 5/5] clk: aspeed: Add reset controller Joel Stanley
2017-12-06  7:56 ` [PATCH v6 0/5] clk: Add Aspeed clock driver Joel Stanley
2017-12-21 23:40   ` Stephen Boyd
2017-12-22  1:42     ` Joel Stanley

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