* [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication
@ 2018-01-02 14:55 Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 1/8] arm64: dts: marvell: fix watchdog unit address in Armada AP806 Thomas Petazzoni
` (8 more replies)
0 siblings, 9 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This series aims at de-duplicating the Armada CP110 Device Tree
description, which is currently duplicated between
armada-cp110-master.dtsi and armada-cp110-slave.dtsi, even though they
are almost identical. Indeed, one concept of Marvell SoCs is that they
are made of HW blocks composed of a variety of IPs (network, PCIe,
SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated
several times within a given SoC. The Armada 7K SoC has a single CP110
(so no duplication), while the Armada 8K SoC has two CP110. In the
future, SoCs with more than 2 CP110s will be introduced.
This duplication issue has been discussed at the DT workshop [1] in
Prague last October, and I presented on this topic [2]. The solution
of using the C pre-processor to avoid this duplication has been
validated by the people present in this DT workshop, and this patch
series simply submits what has been presented.
- The first four patches are fixes for existing
issues/inconsistencies in the Device Tree files. Since they don't
fix any visible problems, they are not marked for -stable.
- The fifth patch is a minor improvement.
- The sixth patch making use of aliases for SPI busses simply aims at
reducing the number of changes between the CP110 master and CP110
slave description, by avoiding the need for the cell-index property
in the SPI controller DT nodes.
- The seventh patch implements the de-duplication itself, by
introducing an armada-cp110.dtsi file included twice on Armada 8K
platforms, once for the master CP110 and once for the slave CP110.
- The last patch renames cpm to cp0 and cps to cp1, as the concept of
master/slave CPs does not apply to future SoCs that have more than
2 CPs.
Changes since v1:
- Rebase on top of mvebu/dt64, since the NAND controller changes will
only be submitted for 4.17.
- Add patches fixing NAND related typos/inconsistencies:
arm64: dts: marvell: fix typos in comment describing the NAND controller
arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
- Improve the de-duplication patch by removing
armada-cp110-master.dtsi and armada-cp110-slave.dtsi, since the
concept of master/slave will no longer exist when we will have more
than 2 CPs.
- Add a patch renaming cpm -> cp0, cps -> cp1.
Best regards,
Thomas
[1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
[2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf
Thomas Petazzoni (8):
arm64: dts: marvell: fix watchdog unit address in Armada AP806
arm64: dts: marvell: use lower case for unit address and reg property
arm64: dts: marvell: fix typos in comment describing the NAND
controller
arm64: dts: marvell: fix compatible string list for Armada CP110 slave
NAND
arm64: dts: marvell: use mvebu-icu.h where possible
arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
arm64: dts: marvell: de-duplicate CP110 description
arm64: dts: marvell: replace cpm by cp0, cps by cp1
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 46 +--
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 37 +-
arch/arm64/boot/dts/marvell/armada-8020.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 80 ++--
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 ++--
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 80 +++-
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 +-
arch/arm64/boot/dts/marvell/armada-common.dtsi | 10 +
.../boot/dts/marvell/armada-cp110-master.dtsi | 449 ---------------------
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 448 --------------------
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 422 +++++++++++++++++++
12 files changed, 635 insertions(+), 1025 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/armada-common.dtsi
delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/armada-cp110.dtsi
--
2.14.3
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/8] arm64: dts: marvell: fix watchdog unit address in Armada AP806
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 2/8] arm64: dts: marvell: use lower case for unit address and reg property Thomas Petazzoni
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
This fixes the following DTC warning:
Warning (simple_bus_reg): Node /ap806/config-space at f0000000/watchdog at 600000 simple-bus unit address format error, expected "610000"
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index bbc5a4d3acac..36f6d7fbb310 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -241,7 +241,7 @@
};
- watchdog: watchdog at 600000 {
+ watchdog: watchdog at 610000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/8] arm64: dts: marvell: use lower case for unit address and reg property
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 1/8] arm64: dts: marvell: fix watchdog unit address in Armada AP806 Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 3/8] arm64: dts: marvell: fix typos in comment describing the NAND controller Thomas Petazzoni
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
This fixes the following DTC warning:
<stdout>: Warning (simple_bus_reg): Node /ap806/config-space at f0000000/thermal at 6f808C simple-bus unit address format error, expected "6f808c"
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 36f6d7fbb310..0575207cafee 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -286,9 +286,9 @@
};
};
- ap_thermal: thermal at 6f808C {
+ ap_thermal: thermal at 6f808c {
compatible = "marvell,armada-ap806-thermal";
- reg = <0x6f808C 0x4>,
+ reg = <0x6f808c 0x4>,
<0x6f8084 0x8>;
};
};
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/8] arm64: dts: marvell: fix typos in comment describing the NAND controller
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 1/8] arm64: dts: marvell: fix watchdog unit address in Armada AP806 Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 2/8] arm64: dts: marvell: use lower case for unit address and reg property Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 4/8] arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND Thomas Petazzoni
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index ecbc76d26dff..a0b2cec2823f 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -317,7 +317,7 @@
cpm_nand: nand at 720000 {
/*
- * Due to the limiation of the pin available
+ * Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 6a07c786b788..0624ec2de496 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -318,7 +318,7 @@
cps_nand: nand at 720000 {
/*
- * Due to the limiation of the pin available
+ * Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/8] arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
` (2 preceding siblings ...)
2018-01-02 14:55 ` [PATCH v2 3/8] arm64: dts: marvell: fix typos in comment describing the NAND controller Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 5/8] arm64: dts: marvell: use mvebu-icu.h where possible Thomas Petazzoni
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
The Armada CP110 slave NAND controller Device Tree description lists
the compatible string in the wrong order: marvell,armada-8k-nand
should come first. This commit alignes the slave CP110 description
with the master CP110 description from that respect.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 0624ec2de496..3eda62d482fc 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -322,8 +322,8 @@
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
- compatible = "marvell,armada370-nand",
- "marvell,armada-8k-nand";
+ compatible = "marvell,armada-8k-nand",
+ "marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/8] arm64: dts: marvell: use mvebu-icu.h where possible
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
` (3 preceding siblings ...)
2018-01-02 14:55 ` [PATCH v2 4/8] arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 6/8] arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K Thomas Petazzoni
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
Back when the ICU Device Tree binding was introduced, we could not use
mvebu-icu.h from the Device Tree files, because the DT files and
mvebu-icu.h were following different merge routes towards Linus
tree. Now that both have been merged, we can switch the Marvell Armada
CP110 Device Tree files to use the mvebu-icu.h header instead of
duplicating the ICU_GRP_NSR definition.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index a0b2cec2823f..f89053577bcc 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -44,7 +44,7 @@
* Device Tree file for Marvell Armada CP110 Master.
*/
-#define ICU_GRP_NSR 0x0
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
/ {
cp110-master {
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 3eda62d482fc..a658b72b0229 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -44,7 +44,7 @@
* Device Tree file for Marvell Armada CP110 Slave.
*/
-#define ICU_GRP_NSR 0x0
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
/ {
cp110-slave {
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 6/8] arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
` (4 preceding siblings ...)
2018-01-02 14:55 ` [PATCH v2 5/8] arm64: dts: marvell: use mvebu-icu.h where possible Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 7/8] arm64: dts: marvell: de-duplicate CP110 description Thomas Petazzoni
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
We are currently using the cell-index DT property to assign SPI bus
numbers. This property is specific to the spi-orion driver, and
requires each SPI controller to have a unique ID defined in the Device
Tree.
As we are about to merge armada-cp110-master.dtsi and
armada-cp110-slave.dtsi into a single file, those cell-index
properties that differ between the master CP110 and the slave CP110
are a difference that would have to be handled.
In order to avoid this, we switch to using the "aliases" DT node to
assign a unique number to each SPI controller. This is more generic,
and directly handled by the SPI core.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ++++
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 --
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 --
5 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 0e1a1e5be399..815e64b3a874 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -50,6 +50,8 @@
aliases {
gpio1 = &cpm_gpio1;
gpio2 = &cpm_gpio2;
+ spi1 = &cpm_spi0;
+ spi2 = &cpm_spi1;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index b280ddd3c397..de9c34333cd4 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -51,6 +51,10 @@
aliases {
gpio1 = &cps_gpio1;
gpio2 = &cpm_gpio2;
+ spi1 = &cpm_spi0;
+ spi2 = &cpm_spi1;
+ spi3 = &cps_spi0;
+ spi4 = &cps_spi1;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 0575207cafee..f9b66b81f9fc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -58,6 +58,7 @@
serial0 = &uart0;
serial1 = &uart1;
gpio0 = &ap_gpio;
+ spi0 = &spi0;
};
psci {
@@ -203,7 +204,6 @@
reg = <0x510600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
- cell-index = <0>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ap_clk 3>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index f89053577bcc..162e6c228bd9 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -280,7 +280,6 @@
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
- cell-index = <1>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
@@ -290,7 +289,6 @@
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
- cell-index = <2>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index a658b72b0229..207b6f444e24 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -281,7 +281,6 @@
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
- cell-index = <3>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
@@ -291,7 +290,6 @@
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
- cell-index = <4>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 7/8] arm64: dts: marvell: de-duplicate CP110 description
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
` (5 preceding siblings ...)
2018-01-02 14:55 ` [PATCH v2 6/8] arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 8/8] arm64: dts: marvell: replace cpm by cp0, cps by cp1 Thomas Petazzoni
2018-01-02 15:31 ` [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Gregory CLEMENT
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
One concept of Marvell Armada 7K/8K SoCs is that they are made of HW
blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI,
I2C, etc.), and those HW blocks can be duplicated several times within
a given SoC. The Armada 7K SoC has a single CP110 (so no duplication),
while the Armada 8K SoC has two CP110. In the future, SoCs with more
than 2 CP110s will be introduced.
In current kernel versions, the master CP110 is described in
armada-cp110-master.dtsi and the slave CP110 is described in
armada-cp110-slave.dtsi. Those files are basically exactly the same,
since they describe the same hardware. They only have a few
differences:
- Base address of the registers is different for the "config-space"
- Base address of the PCIe registers, MEM, CONF and IO areas were
different
- Labels (and phandles pointing to them) of the nodes were different
("cpm" prefix in the master CP, "cps" prefix in the slave CP)
This duplication issue has been discussed at the DT workshop [1] in
Prague last October, and we presented on this topic [2]. The solution
of using the C pre-processor to avoid this duplication has been
validated by the people present in this DT workshop, and this patch
simply implements what has been presented.
We handle differences between the master CP and slave CP description
using the C pre-processor, by defining a set of macros with different
values armada-cp110.dtsi is included to instantiate one of the master
or slave CP110.
There are a few aspects that deserve additional explanations:
- PCIe needs to be handled separately because it is not part of the
config-space {...} node, since it has registers outside of the
range covered by config-space {...}.
- We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because
they are used for the unit address part of some DT nodes. But since
they are also used for the "reg" property of the same nodes, we
have an ADDRESSIFY() macro that prepends 0x to those values.
We compared the resulting .dtb for armada-8040-db.dtb before and after
this patch is applied, and the result is exactly the same, except for
a few differences:
- the SDHCI controller that was only described in the master CP110 is
now also described in the slave CP110. Even though the SDHCI
controller from the slave CP110 is indeed not usable (as it isn't
wired to the outside world) it is technically part of the silicon,
and therefore it is reasonable to also describe it to be part of
the slave CP110. In addition, if we wanted to get this correct for
the SDHCI controller, we should also do it for the NAND controller,
for which the situation is even more complicated: in a single CP110
configuration (Armada 7K), the usable NAND controller is in the
master CP110, while in a dual CP110 configuration (Armada 8K), the
usable NAND controller is in the slave CP110. Since that would add
a lot of additional complexity for no good reason, and since the IP
blocks are in fact really present in both CPs, we simply describe
them in both CPs at the DT level.
- the cp110-master and cp110-slave nodes are now named cpm and
cps. We could have kept cp110-master and cp110-slave, but that
would have required adding another CP110_xyz define, which didn't
seem very useful.
Note that this commit also gets rid of the armada-cp110-master.dtsi
and armada-cp110-slave.dtsi files, as future SoCs will have more than
2 CPs. Instead, we instantiate the CPs directly from the SoC-specific
.dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi.
[1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
[2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 23 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 56 ++-
arch/arm64/boot/dts/marvell/armada-common.dtsi | 10 +
.../boot/dts/marvell/armada-cp110-master.dtsi | 447 ---------------------
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 446 --------------------
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 422 +++++++++++++++++++
6 files changed, 506 insertions(+), 898 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/armada-common.dtsi
delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/armada-cp110.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 815e64b3a874..9917cff3dae6 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -44,8 +44,6 @@
* Device Tree file for the Armada 70x0 SoC
*/
-#include "armada-cp110-master.dtsi"
-
/ {
aliases {
gpio1 = &cpm_gpio1;
@@ -55,6 +53,27 @@
};
};
+/*
+ * Instantiate the CP110
+ */
+#define CP110_NAME cpm
+#define CP110_BASE f2000000
+#define CP110_PCIE_IO_BASE 0xf9000000
+#define CP110_PCIE_MEM_BASE 0xf6000000
+#define CP110_PCIE0_BASE f2600000
+#define CP110_PCIE1_BASE f2620000
+#define CP110_PCIE2_BASE f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
&cpm_gpio1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index de9c34333cd4..5e038e7b7b30 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -44,9 +44,6 @@
* Device Tree file for the Armada 80x0 SoC family
*/
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
-
/ {
aliases {
gpio1 = &cps_gpio1;
@@ -58,6 +55,48 @@
};
};
+/*
+ * Instantiate the master CP110
+ */
+#define CP110_NAME cpm
+#define CP110_BASE f2000000
+#define CP110_PCIE_IO_BASE 0xf9000000
+#define CP110_PCIE_MEM_BASE 0xf6000000
+#define CP110_PCIE0_BASE f2600000
+#define CP110_PCIE1_BASE f2620000
+#define CP110_PCIE2_BASE f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+/*
+ * Instantiate the slave CP110
+ */
+#define CP110_NAME cps
+#define CP110_BASE f4000000
+#define CP110_PCIE_IO_BASE 0xfd000000
+#define CP110_PCIE_MEM_BASE 0xfa000000
+#define CP110_PCIE0_BASE f4600000
+#define CP110_PCIE1_BASE f4620000
+#define CP110_PCIE2_BASE f4640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
/* The 80x0 has two CP blocks, but uses only one block from each. */
&cps_gpio1 {
status = "okay";
@@ -95,3 +134,14 @@
};
};
};
+
+&cps_crypto {
+ /*
+ * The cryptographic engine found on the cp110
+ * master is enabled by default at the SoC
+ * level. Because it is not possible as of now
+ * to enable two cryptographic engines in
+ * parallel, disable this one by default.
+ */
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi
new file mode 100644
index 000000000000..c6dd1d81c68d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
deleted file mode 100644
index 162e6c228bd9..000000000000
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Master.
- */
-
-#include <dt-bindings/interrupt-controller/mvebu-icu.h>
-
-/ {
- cp110-master {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&cpm_icu>;
- ranges;
-
- config-space at f2000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 0xf2000000 0x2000000>;
-
- cpm_ethernet: ethernet at 0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
- clock-names = "pp_clk", "gop_clk", "mg_clk";
- marvell,system-controller = <&cpm_syscon0>;
- status = "disabled";
- dma-coherent;
-
- cpm_eth0: eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- cpm_eth1: eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- cpm_eth2: eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- cpm_comphy: phy at 120000 {
- compatible = "marvell,comphy-cp110";
- reg = <0x120000 0x6000>;
- marvell,system-controller = <&cpm_syscon0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpm_comphy0: phy at 0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- cpm_comphy1: phy at 1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- cpm_comphy2: phy at 2 {
- reg = <2>;
- #phy-cells = <1>;
- };
-
- cpm_comphy3: phy at 3 {
- reg = <3>;
- #phy-cells = <1>;
- };
-
- cpm_comphy4: phy at 4 {
- reg = <4>;
- #phy-cells = <1>;
- };
-
- cpm_comphy5: phy at 5 {
- reg = <5>;
- #phy-cells = <1>;
- };
- };
-
- cpm_mdio: mdio at 12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
- status = "disabled";
- };
-
- cpm_xmdio: mdio at 12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x10>;
- status = "disabled";
- };
-
- cpm_icu: interrupt-controller at 1e0000 {
- compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x10>;
- #interrupt-cells = <3>;
- interrupt-controller;
- msi-parent = <&gicp>;
- };
-
- cpm_rtc: rtc at 284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cpm_thermal: thermal at 400078 {
- compatible = "marvell,armada-cp110-thermal";
- reg = <0x400078 0x4>,
- <0x400070 0x8>;
- };
-
- cpm_syscon0: system-controller at 440000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x440000 0x2000>;
-
- cpm_clk: clock {
- compatible = "marvell,cp110-clock";
- #clock-cells = <2>;
- };
-
- cpm_gpio1: gpio at 100 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x100>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&cpm_pinctrl 0 0 32>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- cpm_gpio2: gpio at 140 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x140>;
- ngpios = <31>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&cpm_pinctrl 0 32 31>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- };
-
- cpm_usb3_0: usb3 at 500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 22>;
- status = "disabled";
- };
-
- cpm_usb3_1: usb3 at 510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 23>;
- status = "disabled";
- };
-
- cpm_sata0: sata at 540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 15>;
- status = "disabled";
- };
-
- cpm_xor0: xor at 6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>,
- <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cpm_clk 1 8>;
- };
-
- cpm_xor1: xor at 6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>,
- <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cpm_clk 1 7>;
- };
-
- cpm_spi0: spi at 700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- clocks = <&cpm_clk 1 21>;
- status = "disabled";
- };
-
- cpm_spi1: spi at 700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cpm_clk 1 21>;
- status = "disabled";
- };
-
- cpm_i2c0: i2c at 701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 21>;
- status = "disabled";
- };
-
- cpm_i2c1: i2c at 701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 21>;
- status = "disabled";
- };
-
- cpm_nand: nand at 720000 {
- /*
- * Due to the limitation of the pins available
- * this controller is only usable on the CPM
- * for A7K and on the CPS for A8K.
- */
- compatible = "marvell,armada-8k-nand",
- "marvell,armada370-nand";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 2>;
- marvell,system-controller = <&cpm_syscon0>;
- status = "disabled";
- };
-
- cpm_trng: trng at 760000 {
- compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
- reg = <0x760000 0x7d>;
- interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_clk 1 25>;
- status = "okay";
- };
-
- cpm_sdhci0: sdhci at 780000 {
- compatible = "marvell,armada-cp110-sdhci";
- reg = <0x780000 0x300>;
- interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core";
- clocks = <&cpm_clk 1 4>;
- dma-coherent;
- status = "disabled";
- };
-
- cpm_crypto: crypto at 800000 {
- compatible = "inside-secure,safexcel-eip197";
- reg = <0x800000 0x200000>;
- interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
- clocks = <&cpm_clk 1 26>;
- dma-coherent;
- };
- };
-
- cpm_pcie0: pcie at f2600000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2600000 0 0x10000>,
- <0 0xf6f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clocks = <&cpm_clk 1 13>;
- status = "disabled";
- };
-
- cpm_pcie1: pcie at f2620000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2620000 0 0x10000>,
- <0 0xf7f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cpm_clk 1 11>;
- status = "disabled";
- };
-
- cpm_pcie2: pcie at f2640000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2640000 0 0x10000>,
- <0 0xf8f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cpm_clk 1 12>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
deleted file mode 100644
index 207b6f444e24..000000000000
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Slave.
- */
-
-#include <dt-bindings/interrupt-controller/mvebu-icu.h>
-
-/ {
- cp110-slave {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&cps_icu>;
- ranges;
-
- config-space at f4000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 0xf4000000 0x2000000>;
-
- cps_ethernet: ethernet at 0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
- clock-names = "pp_clk", "gop_clk", "mg_clk";
- marvell,system-controller = <&cps_syscon0>;
- status = "disabled";
- dma-coherent;
-
- cps_eth0: eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- cps_eth1: eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- cps_eth2: eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
- "tx-cpu3", "rx-shared", "link";
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- cps_comphy: phy at 120000 {
- compatible = "marvell,comphy-cp110";
- reg = <0x120000 0x6000>;
- marvell,system-controller = <&cps_syscon0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- cps_comphy0: phy at 0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- cps_comphy1: phy at 1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- cps_comphy2: phy at 2 {
- reg = <2>;
- #phy-cells = <1>;
- };
-
- cps_comphy3: phy at 3 {
- reg = <3>;
- #phy-cells = <1>;
- };
-
- cps_comphy4: phy at 4 {
- reg = <4>;
- #phy-cells = <1>;
- };
-
- cps_comphy5: phy at 5 {
- reg = <5>;
- #phy-cells = <1>;
- };
- };
-
- cps_mdio: mdio at 12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
- status = "disabled";
- };
-
- cps_xmdio: mdio at 12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x10>;
- status = "disabled";
- };
-
- cps_icu: interrupt-controller at 1e0000 {
- compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x10>;
- #interrupt-cells = <3>;
- interrupt-controller;
- msi-parent = <&gicp>;
- };
-
- cps_rtc: rtc at 284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cps_thermal: thermal at 400078 {
- compatible = "marvell,armada-cp110-thermal";
- reg = <0x400078 0x4>,
- <0x400070 0x8>;
- };
-
- cps_syscon0: system-controller at 440000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x440000 0x2000>;
-
- cps_clk: clock {
- compatible = "marvell,cp110-clock";
- #clock-cells = <2>;
- };
-
- cps_gpio1: gpio at 100 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x100>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&cps_pinctrl 0 0 32>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- cps_gpio2: gpio at 140 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x140>;
- ngpios = <31>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&cps_pinctrl 0 32 31>;
- interrupt-controller;
- interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- };
-
- cps_usb3_0: usb3 at 500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 22>;
- status = "disabled";
- };
-
- cps_usb3_1: usb3 at 510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 23>;
- status = "disabled";
- };
-
- cps_sata0: sata at 540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 15>;
- status = "disabled";
- };
-
- cps_xor0: xor at 6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>,
- <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cps_clk 1 8>;
- };
-
- cps_xor1: xor at 6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>,
- <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cps_clk 1 7>;
- };
-
- cps_spi0: spi at 700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- clocks = <&cps_clk 1 21>;
- status = "disabled";
- };
-
- cps_spi1: spi at 700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&cps_clk 1 21>;
- status = "disabled";
- };
-
- cps_i2c0: i2c at 701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 21>;
- status = "disabled";
- };
-
- cps_i2c1: i2c at 701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 21>;
- status = "disabled";
- };
-
- cps_nand: nand at 720000 {
- /*
- * Due to the limitation of the pins available
- * this controller is only usable on the CPM
- * for A7K and on the CPS for A8K.
- */
- compatible = "marvell,armada-8k-nand",
- "marvell,armada370-nand";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 2>;
- marvell,system-controller = <&cpm_syscon0>;
- status = "disabled";
- };
-
- cps_trng: trng at 760000 {
- compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
- reg = <0x760000 0x7d>;
- interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_clk 1 25>;
- status = "okay";
- };
-
- cps_crypto: crypto at 800000 {
- compatible = "inside-secure,safexcel-eip197";
- reg = <0x800000 0x200000>;
- interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
- clocks = <&cps_clk 1 26>;
- dma-coherent;
- /*
- * The cryptographic engine found on the cp110
- * master is enabled by default at the SoC
- * level. Because it is not possible as of now
- * to enable two cryptographic engines in
- * parallel, disable this one by default.
- */
- status = "disabled";
- };
- };
-
- cps_pcie0: pcie at f4600000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4600000 0 0x10000>,
- <0 0xfaf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clocks = <&cps_clk 1 13>;
- status = "disabled";
- };
-
- cps_pcie1: pcie at f4620000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4620000 0 0x10000>,
- <0 0xfbf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cps_clk 1 11>;
- status = "disabled";
- };
-
- cps_pcie2: pcie at f4640000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4640000 0 0x10000>,
- <0 0xfcf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cps_clk 1 12>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
new file mode 100644
index 000000000000..08989a158578
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/*
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+
+#include "armada-common.dtsi"
+
+#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
+#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+/ {
+ /*
+ * The contents of the node are defined below, in order to
+ * save one indentation level
+ */
+ CP110_NAME: CP110_NAME { };
+};
+
+&CP110_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&CP110_LABEL(icu)>;
+ ranges;
+
+ config-space at CP110_BASE {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
+
+ CP110_LABEL(ethernet): ethernet at 0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
+ <&CP110_LABEL(clk) 1 5>;
+ clock-names = "pp_clk", "gop_clk", "mg_clk";
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ dma-coherent;
+
+ CP110_LABEL(eth0): eth0 {
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth1): eth1 {
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth2): eth2 {
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(comphy): phy at 120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CP110_LABEL(comphy0): phy at 0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy1): phy at 1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy2): phy at 2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy3): phy at 3 {
+ reg = <3>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy4): phy at 4 {
+ reg = <4>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy5): phy at 5 {
+ reg = <5>;
+ #phy-cells = <1>;
+ };
+ };
+
+ CP110_LABEL(mdio): mdio at 12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xmdio): mdio at 12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(icu): interrupt-controller at 1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP110_LABEL(rtc): rtc at 284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ CP110_LABEL(thermal): thermal at 400078 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x400078 0x4>,
+ <0x400070 0x8>;
+ };
+
+ CP110_LABEL(syscon0): system-controller at 440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+
+ CP110_LABEL(clk): clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
+
+ CP110_LABEL(gpio1): gpio at 100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(gpio2): gpio at 140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(usb3_0): usb3 at 500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 22>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_1): usb3 at 510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 23>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(sata0): sata at 540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 15>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xor0): xor at 6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&CP110_LABEL(clk) 1 8>;
+ };
+
+ CP110_LABEL(xor1): xor at 6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&CP110_LABEL(clk) 1 7>;
+ };
+
+ CP110_LABEL(spi0): spi at 700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clocks = <&CP110_LABEL(clk) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi1): spi at 700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&CP110_LABEL(clk) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c0): i2c at 701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c1): i2c at 701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand): nand at 720000 {
+ /*
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada-8k-nand",
+ "marvell,armada370-nand";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 2>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(trng): trng at 760000 {
+ compatible = "marvell,armada-8k-rng",
+ "inside-secure,safexcel-eip76";
+ reg = <0x760000 0x7d>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(clk) 1 25>;
+ status = "okay";
+ };
+
+ CP110_LABEL(sdhci0): sdhci at 780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&CP110_LABEL(clk) 1 4>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP110_LABEL(crypto): crypto at 800000 {
+ compatible = "inside-secure,safexcel-eip197";
+ reg = <0x800000 0x200000>;
+ interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clocks = <&CP110_LABEL(clk) 1 26>;
+ dma-coherent;
+ };
+ };
+
+ CP110_LABEL(pcie0): pcie at CP110_PCIE0_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(clk) 1 13>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie1): pcie at CP110_PCIE1_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(clk) 1 11>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie2): pcie at CP110_PCIE2_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(clk) 1 12>;
+ status = "disabled";
+ };
+};
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 8/8] arm64: dts: marvell: replace cpm by cp0, cps by cp1
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
` (6 preceding siblings ...)
2018-01-02 14:55 ` [PATCH v2 7/8] arm64: dts: marvell: de-duplicate CP110 description Thomas Petazzoni
@ 2018-01-02 14:55 ` Thomas Petazzoni
2018-01-02 15:31 ` [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Gregory CLEMENT
8 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In preparation for the introduction of more than 2 CPs in upcoming
SoCs, it makes sense to move away from the "CP master" (cpm) and "CP
slave" (cps) naming, and use instead cp0/cp1.
This commit is the result of:
sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/*
sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/*
So it is a purely mechaninal change.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Suggested-by: Hanna Hawa <hannah@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 46 ++++++-------
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 18 ++---
arch/arm64/boot/dts/marvell/armada-8020.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 80 +++++++++++------------
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 ++++++++++-----------
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 34 +++++-----
7 files changed, 129 insertions(+), 129 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 52b5341cb270..44c95b97a422 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -61,7 +61,7 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+ cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h0-vbus";
regulator-min-microvolt = <5000000>;
@@ -70,7 +70,7 @@
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
- cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+ cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h1-vbus";
regulator-min-microvolt = <5000000>;
@@ -79,14 +79,14 @@
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
- cpm_usb3_0_phy: cpm-usb3-0-phy {
+ cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_0_vbus>;
+ vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
- cpm_usb3_1_phy: cpm-usb3-1-phy {
+ cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_1_vbus>;
+ vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
};
@@ -129,11 +129,11 @@
};
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -156,7 +156,7 @@
};
};
-&cpm_nand {
+&cp0_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
@@ -186,7 +186,7 @@
};
-&cpm_spi1 {
+&cp0_spi1 {
status = "okay";
spi-flash at 0 {
@@ -214,17 +214,17 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_usb3_0 {
- usb-phy = <&cpm_usb3_0_phy>;
+&cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
-&cpm_usb3_1 {
- usb-phy = <&cpm_usb3_1_phy>;
+&cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
@@ -235,14 +235,14 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
-&cpm_mdio {
+&cp0_mdio {
status = "okay";
phy0: ethernet-phy at 0 {
@@ -253,28 +253,28 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
- phys = <&cpm_comphy2 0>;
+ phys = <&cp0_comphy2 0>;
};
-&cpm_eth1 {
+&cp0_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
- phys = <&cpm_comphy0 1>;
+ phys = <&cp0_comphy0 1>;
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 9917cff3dae6..f63b4fbd642b 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -46,17 +46,17 @@
/ {
aliases {
- gpio1 = &cpm_gpio1;
- gpio2 = &cpm_gpio2;
- spi1 = &cpm_spi0;
- spi2 = &cpm_spi1;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
};
};
/*
* Instantiate the CP110
*/
-#define CP110_NAME cpm
+#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
@@ -74,16 +74,16 @@
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
-&cpm_gpio1 {
+&cp0_gpio1 {
status = "okay";
};
-&cpm_gpio2 {
+&cp0_gpio2 {
status = "okay";
};
-&cpm_syscon0 {
- cpm_pinctrl: pinctrl {
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
nand_pins: nand-pins {
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 0ba0bc942598..3318d6b0214b 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -60,6 +60,6 @@
* oscillator so this one is let enabled.
*/
-&cpm_rtc {
+&cp0_rtc {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index b1f6cccc5081..13e3209d554a 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -61,46 +61,46 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+ cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
- regulator-name = "cpm-usb3h0-vbus";
+ regulator-name = "cp0-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
- cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+ cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
- regulator-name = "cpm-usb3h1-vbus";
+ regulator-name = "cp0-usb3h1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
- cpm_usb3_0_phy: cpm-usb3-0-phy {
+ cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_0_vbus>;
+ vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
- cpm_usb3_1_phy: cpm-usb3-1-phy {
+ cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_1_vbus>;
+ vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
- cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
+ cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
compatible = "regulator-fixed";
- regulator-name = "cps-usb3h0-vbus";
+ regulator-name = "cp1-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
};
- cps_usb3_0_phy: cps-usb3-0-phy {
+ cp1_usb3_0_phy: cp1-usb3-0-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cps_reg_usb3_0_vbus>;
+ vcc-supply = <&cp1_reg_usb3_0_vbus>;
};
};
@@ -144,16 +144,16 @@
};
/* CON6 on CP0 expansion */
-&cpm_pcie0 {
+&cp0_pcie0 {
status = "okay";
};
/* CON5 on CP0 expansion */
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -178,23 +178,23 @@
};
/* CON4 on CP0 expansion */
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
-&cpm_usb3_0 {
- usb-phy = <&cpm_usb3_0_phy>;
+&cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP0 expansion */
-&cpm_usb3_1 {
- usb-phy = <&cpm_usb3_1_phy>;
+&cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
status = "okay";
phy1: ethernet-phy at 1 {
@@ -202,42 +202,42 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON6 on CP1 expansion */
-&cps_pcie0 {
+&cp1_pcie0 {
status = "okay";
};
/* CON7 on CP1 expansion */
-&cps_pcie1 {
+&cp1_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
-&cps_pcie2 {
+&cp1_pcie2 {
status = "okay";
};
-&cps_i2c0 {
+&cp1_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
-&cps_spi1 {
+&cp1_spi1 {
status = "okay";
spi-flash at 0 {
@@ -272,14 +272,14 @@
* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
* MDIO signal of CP1.
*/
-&cps_nand {
+&cp1_nand {
num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
- marvell,system-controller = <&cps_syscon0>;
+ marvell,system-controller = <&cp1_syscon0>;
nand-on-flash-bbt;
partition at 0 {
@@ -297,22 +297,22 @@
};
/* CON4 on CP1 expansion */
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
-&cps_usb3_0 {
- usb-phy = <&cps_usb3_0_phy>;
+&cp1_usb3_0 {
+ usb-phy = <&cp1_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP1 expansion */
-&cps_usb3_1 {
+&cp1_usb3_1 {
status = "okay";
};
-&cps_mdio {
+&cp1_mdio {
status = "okay";
phy0: ethernet-phy at 0 {
@@ -320,16 +320,16 @@
};
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth0 {
+&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
@@ -341,7 +341,7 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index b3350827ee55..c7aca67bd244 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -84,9 +84,9 @@
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
+ gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -120,17 +120,17 @@
vqmmc-supply = <&v_vddo_h>;
};
-&cpm_i2c0 {
+&cp0_i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
};
-&cpm_i2c1 {
+&cp0_i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
i2c-switch at 70 {
@@ -157,9 +157,9 @@
};
};
-&cpm_mdio {
+&cp0_mdio {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_ge_mdio_pins>;
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
status = "okay";
ge_phy: ethernet-phy at 0 {
@@ -167,44 +167,44 @@
};
};
-&cpm_pcie0 {
+&cp0_pcie0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_pins>;
+ pinctrl-0 = <&cp0_pcie_pins>;
num-lanes = <4>;
num-viewport = <8>;
- reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
-&cpm_pinctrl {
- cpm_ge_mdio_pins: ge-mdio-pins {
+&cp0_pinctrl {
+ cp0_ge_mdio_pins: ge-mdio-pins {
marvell,pins = "mpp32", "mpp34";
marvell,function = "ge";
};
- cpm_i2c1_pins: i2c1-pins {
+ cp0_i2c1_pins: i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
- cpm_i2c0_pins: i2c0-pins {
+ cp0_i2c0_pins: i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
- cpm_xhci_vbus_pins: xhci0-vbus-pins {
+ cp0_xhci_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
- cpm_pcie_pins: pcie-pins {
+ cp0_pcie_pins: pcie-pins {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
- cpm_sdhci_pins: sdhci-pins {
+ cp0_sdhci_pins: sdhci-pins {
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
"mpp60", "mpp61";
marvell,function = "sdio";
};
};
-&cpm_xmdio {
+&cp0_xmdio {
status = "okay";
phy0: ethernet-phy at 0 {
@@ -218,83 +218,83 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
- phys = <&cpm_comphy4 0>;
+ phys = <&cp0_comphy4 0>;
};
-&cpm_sata0 {
+&cp0_sata0 {
/* CPM Lane 0 - U29 */
status = "okay";
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
/* U6 */
broken-cd;
bus-width = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
-&cpm_usb3_0 {
+&cp0_usb3_0 {
/* J38? - USB2.0 only */
status = "okay";
};
-&cpm_usb3_1 {
+&cp0_usb3_1 {
/* J38? - USB2.0 only */
status = "okay";
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth0 {
+&cp1_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
- phys = <&cps_comphy4 0>;
+ phys = <&cp1_comphy4 0>;
};
-&cps_eth1 {
+&cp1_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
/* Network PHY */
phy = <&ge_phy>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
- phys = <&cps_comphy0 1>;
+ phys = <&cp1_comphy0 1>;
};
-&cps_pinctrl {
- cps_spi1_pins: spi1-pins {
+&cp1_pinctrl {
+ cp1_spi1_pins: spi1-pins {
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
-&cps_sata0 {
+&cp1_sata0 {
/* CPS Lane 1 - U32 */
/* CPS Lane 3 - U31 */
status = "okay";
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash at 0 {
@@ -304,7 +304,7 @@
};
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
usb-phy = <&usb3h0_phy>;
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 60fe84f5cbcc..83d2b40e5981 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -59,6 +59,6 @@
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
-&cpm_rtc {
+&cp0_rtc {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 5e038e7b7b30..0d36b0fa7153 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -46,19 +46,19 @@
/ {
aliases {
- gpio1 = &cps_gpio1;
- gpio2 = &cpm_gpio2;
- spi1 = &cpm_spi0;
- spi2 = &cpm_spi1;
- spi3 = &cps_spi0;
- spi4 = &cps_spi1;
+ gpio1 = &cp1_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ spi3 = &cp1_spi0;
+ spi4 = &cp1_spi1;
};
};
/*
* Instantiate the master CP110
*/
-#define CP110_NAME cpm
+#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
@@ -79,7 +79,7 @@
/*
* Instantiate the slave CP110
*/
-#define CP110_NAME cps
+#define CP110_NAME cp1
#define CP110_BASE f4000000
#define CP110_PCIE_IO_BASE 0xfd000000
#define CP110_PCIE_MEM_BASE 0xfa000000
@@ -98,23 +98,23 @@
#undef CP110_PCIE2_BASE
/* The 80x0 has two CP blocks, but uses only one block from each. */
-&cps_gpio1 {
+&cp1_gpio1 {
status = "okay";
};
-&cpm_gpio2 {
+&cp0_gpio2 {
status = "okay";
};
-&cpm_syscon0 {
- cpm_pinctrl: pinctrl {
- compatible = "marvell,armada-8k-cpm-pinctrl";
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cp0-pinctrl";
};
};
-&cps_syscon0 {
- cps_pinctrl: pinctrl {
- compatible = "marvell,armada-8k-cps-pinctrl";
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cp1-pinctrl";
nand_pins: nand-pins {
marvell,pins =
@@ -135,7 +135,7 @@
};
};
-&cps_crypto {
+&cp1_crypto {
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC
--
2.14.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
` (7 preceding siblings ...)
2018-01-02 14:55 ` [PATCH v2 8/8] arm64: dts: marvell: replace cpm by cp0, cps by cp1 Thomas Petazzoni
@ 2018-01-02 15:31 ` Gregory CLEMENT
2018-01-02 16:07 ` Thomas Petazzoni
8 siblings, 1 reply; 11+ messages in thread
From: Gregory CLEMENT @ 2018-01-02 15:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi Thomas,
On mar., janv. 02 2018, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote:
> Hello,
>
> This series aims at de-duplicating the Armada CP110 Device Tree
> description, which is currently duplicated between
> armada-cp110-master.dtsi and armada-cp110-slave.dtsi, even though they
> are almost identical. Indeed, one concept of Marvell SoCs is that they
> are made of HW blocks composed of a variety of IPs (network, PCIe,
> SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated
> several times within a given SoC. The Armada 7K SoC has a single CP110
> (so no duplication), while the Armada 8K SoC has two CP110. In the
> future, SoCs with more than 2 CP110s will be introduced.
>
> This duplication issue has been discussed at the DT workshop [1] in
> Prague last October, and I presented on this topic [2]. The solution
> of using the C pre-processor to avoid this duplication has been
> validated by the people present in this DT workshop, and this patch
> series simply submits what has been presented.
>
> - The first four patches are fixes for existing
> issues/inconsistencies in the Device Tree files. Since they don't
> fix any visible problems, they are not marked for -stable.
>
> - The fifth patch is a minor improvement.
>
> - The sixth patch making use of aliases for SPI busses simply aims at
> reducing the number of changes between the CP110 master and CP110
> slave description, by avoiding the need for the cell-index property
> in the SPI controller DT nodes.
>
> - The seventh patch implements the de-duplication itself, by
> introducing an armada-cp110.dtsi file included twice on Armada 8K
> platforms, once for the master CP110 and once for the slave CP110.
>
> - The last patch renames cpm to cp0 and cps to cp1, as the concept of
> master/slave CPs does not apply to future SoCs that have more than
> 2 CPs.
>
> Changes since v1:
>
> - Rebase on top of mvebu/dt64, since the NAND controller changes will
> only be submitted for 4.17.
>
> - Add patches fixing NAND related typos/inconsistencies:
> arm64: dts: marvell: fix typos in comment describing the NAND controller
> arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
>
> - Improve the de-duplication patch by removing
> armada-cp110-master.dtsi and armada-cp110-slave.dtsi, since the
> concept of master/slave will no longer exist when we will have more
> than 2 CPs.
>
> - Add a patch renaming cpm -> cp0, cps -> cp1.
>
> Best regards,
>
> Thomas
>
I applied all the series on mvebu/dt64. The only change I made was
adding a commit log to the patch 3:
"Fix the same typo duplicated in both master and slave version of
armada-cp110-*.dtsi file: s/limiation/limitation/."
Thanks,
Gregory
> [1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
> [2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf
>
> Thomas Petazzoni (8):
> arm64: dts: marvell: fix watchdog unit address in Armada AP806
> arm64: dts: marvell: use lower case for unit address and reg property
> arm64: dts: marvell: fix typos in comment describing the NAND
> controller
> arm64: dts: marvell: fix compatible string list for Armada CP110 slave
> NAND
> arm64: dts: marvell: use mvebu-icu.h where possible
> arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
> arm64: dts: marvell: de-duplicate CP110 description
> arm64: dts: marvell: replace cpm by cp0, cps by cp1
>
> arch/arm64/boot/dts/marvell/armada-7040-db.dts | 46 +--
> arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 37 +-
> arch/arm64/boot/dts/marvell/armada-8020.dtsi | 2 +-
> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 80 ++--
> arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 ++--
> arch/arm64/boot/dts/marvell/armada-8040.dtsi | 2 +-
> arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 80 +++-
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 +-
> arch/arm64/boot/dts/marvell/armada-common.dtsi | 10 +
> .../boot/dts/marvell/armada-cp110-master.dtsi | 449 ---------------------
> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 448 --------------------
> arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 422 +++++++++++++++++++
> 12 files changed, 635 insertions(+), 1025 deletions(-)
> create mode 100644 arch/arm64/boot/dts/marvell/armada-common.dtsi
> delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/armada-cp110.dtsi
>
> --
> 2.14.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication
2018-01-02 15:31 ` [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Gregory CLEMENT
@ 2018-01-02 16:07 ` Thomas Petazzoni
0 siblings, 0 replies; 11+ messages in thread
From: Thomas Petazzoni @ 2018-01-02 16:07 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Tue, 02 Jan 2018 16:31:32 +0100, Gregory CLEMENT wrote:
> I applied all the series on mvebu/dt64. The only change I made was
> adding a commit log to the patch 3:
> "Fix the same typo duplicated in both master and slave version of
> armada-cp110-*.dtsi file: s/limiation/limitation/."
Thanks!
I would recommend you to ask people submitting DT changes for this
cycle to base their changes on your mvebu/dt64 branch, because most DT
changes for 7K/8K are going to conflict with this de-duplication +
renaming patch series.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-01-02 16:07 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-01-02 14:55 [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 1/8] arm64: dts: marvell: fix watchdog unit address in Armada AP806 Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 2/8] arm64: dts: marvell: use lower case for unit address and reg property Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 3/8] arm64: dts: marvell: fix typos in comment describing the NAND controller Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 4/8] arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 5/8] arm64: dts: marvell: use mvebu-icu.h where possible Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 6/8] arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 7/8] arm64: dts: marvell: de-duplicate CP110 description Thomas Petazzoni
2018-01-02 14:55 ` [PATCH v2 8/8] arm64: dts: marvell: replace cpm by cp0, cps by cp1 Thomas Petazzoni
2018-01-02 15:31 ` [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication Gregory CLEMENT
2018-01-02 16:07 ` Thomas Petazzoni
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