From: vinod.koul@intel.com (Vinod Koul)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly
Date: Mon, 8 Jan 2018 16:08:45 +0530 [thread overview]
Message-ID: <20180108103845.GE18649@localhost> (raw)
In-Reply-To: <1514961731-1916-2-git-send-email-appanad@xilinx.com>
On Wed, Jan 03, 2018 at 12:12:08PM +0530, Kedareswara rao Appana wrote:
> When client driver uses dma_get_slave_caps() api,
> it checks for certain fields of dma_device struct
> currently driver is not settings the directions and addr_widths
> fields resulting dma_get_slave_caps() returning failure.
>
> This patch fixes this issue by populating proper values
> to the struct dma_device directions and addr_widths fields.
>
> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
> ---
> Changes for v2:
> --> Improved commit message title and description
> as suggested by Vinod.
>
> drivers/dma/xilinx/xilinx_dma.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 88d317d..21ac954 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
> chan->direction = DMA_MEM_TO_DEV;
> chan->id = chan_id;
> chan->tdest = chan_id;
> + xdev->common.directions = BIT(DMA_MEM_TO_DEV);
>
> chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
> @@ -2415,6 +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
> chan->direction = DMA_DEV_TO_MEM;
> chan->id = chan_id;
> chan->tdest = chan_id - xdev->nr_channels;
> + xdev->common.directions |= BIT(DMA_DEV_TO_MEM);
>
> chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
> @@ -2629,6 +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
> dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
> }
>
> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
> + xdev->common.src_addr_widths = BIT(addr_width / 8);
Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? What is
value of addr_width here typically? Usually controllers can support
different widths and this is a surprise that you support only one value
--
~Vinod
next prev parent reply other threads:[~2018-01-08 10:38 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-03 6:42 [PATCH v2 0/4] dmaengine: xilinx_dma: Bug fixes Kedareswara rao Appana
2018-01-03 6:42 ` [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Kedareswara rao Appana
2018-01-08 10:38 ` Vinod Koul [this message]
2018-01-08 10:52 ` Appana Durga Kedareswara Rao
2018-01-08 17:06 ` Vinod Koul
2018-01-08 17:25 ` Appana Durga Kedareswara Rao
2018-01-09 4:48 ` Vinod Koul
2018-01-09 4:48 ` Appana Durga Kedareswara Rao
2018-01-09 5:04 ` Vinod Koul
2018-01-09 7:36 ` Appana Durga Kedareswara Rao
2018-01-11 6:21 ` Vinod Koul
2018-01-03 6:42 ` [PATCH v2 2/4] dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma Kedareswara rao Appana
2018-01-08 10:55 ` Vinod Koul
2018-01-03 6:42 ` [PATCH v2 3/4] dmaengine: xilinx_dma: Fix warning variable prev set but not used Kedareswara rao Appana
2018-01-03 6:42 ` [PATCH v2 4/4] dmaengine: xilinx_dma: Free BD consistent memory Kedareswara rao Appana
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