From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Mon, 8 Jan 2018 22:36:55 +0530 Subject: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly In-Reply-To: References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> Message-ID: <20180108170655.GJ18649@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Jan 08, 2018 at 10:52:01AM +0000, Appana Durga Kedareswara Rao wrote: > Hi Vinod, > > Thanks for the review.... > > >> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct > >xilinx_dma_device *xdev, > >> chan->direction = DMA_MEM_TO_DEV; > >> chan->id = chan_id; > >> chan->tdest = chan_id; > >> + xdev->common.directions = BIT(DMA_MEM_TO_DEV); > >> > >> chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2415,6 > >> +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > >> chan->direction = DMA_DEV_TO_MEM; > >> chan->id = chan_id; > >> chan->tdest = chan_id - xdev->nr_channels; > >> + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); > >> > >> chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2629,6 > >> +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) > >> dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); > >> } > >> > >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > > > >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? What is value > >of addr_width here typically? Usually controllers can support different widths and > >this is a surprise that you support only one value > > Controller supports address width of 32 and 64. Then this should have both 32 and 64 values here > addr_width typical values are 32-bit or 64-bit . > Here addr_width is device-tree parameter... > my understanding of src_addr_widths/dst_addr_widths is, it is a bit mask of the > address with in bytes that DMA supports, please correct if my understanding is wrong. > > Regards, > Kedar. > > > > >-- > >~Vinod -- ~Vinod