From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@bootlin.com (Maxime Ripard) Date: Mon, 5 Mar 2018 11:04:31 +0100 Subject: [PATCH 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller In-Reply-To: <20180305100432.15009-1-maxime.ripard@bootlin.com> References: <20180305100432.15009-1-maxime.ripard@bootlin.com> Message-ID: <20180305100432.15009-4-maxime.ripard@bootlin.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Myl?ne Josserand The H3 and H5 features the same CSI controller that was initially found on the A31. Add a DT node for it. Signed-off-by: Myl?ne Josserand Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 7a83b15225c7..fc538fd8282a 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -325,6 +325,13 @@ interrupt-controller; #interrupt-cells = <3>; + csi_pins: csi { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE10", "PE11"; + function = "csi"; + }; + emac_rgmii_pins: emac0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", @@ -684,6 +691,21 @@ interrupts = ; }; + csi: camera at 1cb0000 { + compatible = "allwinner,sun8i-h3-csi", + "allwinner,sun6i-a31-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + rtc: rtc at 1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; -- 2.14.3