From: alex.shi@linaro.org (Alex Shi)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 21/39] arm64: Implement branch predictor hardening for affected Cortex-A CPUs
Date: Fri, 9 Mar 2018 17:07:04 +0800 [thread overview]
Message-ID: <20180309090722.26279-22-alex.shi@linaro.org> (raw)
In-Reply-To: <20180309090722.26279-1-alex.shi@linaro.org>
From: Will Deacon <will.deacon@arm.com>
commit aa6acde65e03 upstream.
Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing
and can theoretically be attacked by malicious code.
This patch implements a PSCI-based mitigation for these CPUs when available.
The call into firmware will invalidate the branch predictor state, preventing
any malicious entries from affecting other victim contexts.
Co-developed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Alex Shi <alex.shi@linaro.org>
---
arch/arm64/kernel/bpi.S | 24 +++++++++++++++++++
arch/arm64/kernel/cpu_errata.c | 42 ++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S
index 06a931eb2673..dec95bd82e31 100644
--- a/arch/arm64/kernel/bpi.S
+++ b/arch/arm64/kernel/bpi.S
@@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start)
vectors __kvm_hyp_vector
.endr
ENTRY(__bp_harden_hyp_vecs_end)
+ENTRY(__psci_hyp_bp_inval_start)
+ sub sp, sp, #(8 * 18)
+ stp x16, x17, [sp, #(16 * 0)]
+ stp x14, x15, [sp, #(16 * 1)]
+ stp x12, x13, [sp, #(16 * 2)]
+ stp x10, x11, [sp, #(16 * 3)]
+ stp x8, x9, [sp, #(16 * 4)]
+ stp x6, x7, [sp, #(16 * 5)]
+ stp x4, x5, [sp, #(16 * 6)]
+ stp x2, x3, [sp, #(16 * 7)]
+ stp x0, x1, [sp, #(16 * 8)]
+ mov x0, #0x84000000
+ smc #0
+ ldp x16, x17, [sp, #(16 * 0)]
+ ldp x14, x15, [sp, #(16 * 1)]
+ ldp x12, x13, [sp, #(16 * 2)]
+ ldp x10, x11, [sp, #(16 * 3)]
+ ldp x8, x9, [sp, #(16 * 4)]
+ ldp x6, x7, [sp, #(16 * 5)]
+ ldp x4, x5, [sp, #(16 * 6)]
+ ldp x2, x3, [sp, #(16 * 7)]
+ ldp x0, x1, [sp, #(16 * 8)]
+ add sp, sp, #(8 * 18)
+ENTRY(__psci_hyp_bp_inval_end)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index b84a93e8c8bd..3adbbce7334c 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -36,6 +36,8 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
#ifdef CONFIG_KVM
+extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[];
+
static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
const char *hyp_vecs_end)
{
@@ -77,6 +79,9 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
spin_unlock(&bp_lock);
}
#else
+#define __psci_hyp_bp_inval_start NULL
+#define __psci_hyp_bp_inval_end NULL
+
static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
const char *hyp_vecs_start,
const char *hyp_vecs_end)
@@ -98,6 +103,21 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
}
+
+#include <linux/psci.h>
+
+static int enable_psci_bp_hardening(void *data)
+{
+ const struct arm64_cpu_capabilities *entry = data;
+
+ if (psci_ops.get_version)
+ install_bp_hardening_cb(entry,
+ (bp_hardening_cb_t)psci_ops.get_version,
+ __psci_hyp_bp_inval_start,
+ __psci_hyp_bp_inval_end);
+
+ return 0;
+}
#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
#define MIDR_RANGE(model, min, max) \
@@ -173,6 +193,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
MIDR_RANGE(MIDR_THUNDERX, 0x00,
(1 << MIDR_VARIANT_SHIFT) | 1),
},
+#endif
+#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
+ {
+ .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
+ .enable = enable_psci_bp_hardening,
+ },
+ {
+ .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
+ .enable = enable_psci_bp_hardening,
+ },
+ {
+ .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+ .enable = enable_psci_bp_hardening,
+ },
+ {
+ .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
+ .enable = enable_psci_bp_hardening,
+ },
#endif
{
}
--
2.16.2.440.gc6284da
next prev parent reply other threads:[~2018-03-09 9:07 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-09 9:06 spectre backport for LTS 4.4 review Alex Shi
2018-03-09 9:06 ` [PATCH 01/39] mm: Introduce lm_alias Alex Shi
2018-03-09 9:06 ` [PATCH 02/39] arm64: barrier: Add CSDB macros to control data-value prediction Alex Shi
2018-03-09 9:06 ` [PATCH 03/39] arm64: Implement array_index_mask_nospec() Alex Shi
2018-03-09 9:06 ` [PATCH 04/39] arm64: move TASK_* definitions to <asm/processor.h> Alex Shi
2018-03-09 9:06 ` [PATCH 05/39] arm64: Make USER_DS an inclusive limit Alex Shi
2018-03-09 9:06 ` [PATCH 06/39] arm64: entry: Ensure branch through syscall table is bounded under speculation Alex Shi
2018-03-09 9:06 ` [PATCH 07/39] arm64: Use pointer masking to limit uaccess speculation Alex Shi
2018-03-09 9:06 ` [PATCH 08/39] arm64: uaccess: Prevent speculative use of the current addr_limit Alex Shi
2018-03-09 9:06 ` [PATCH 09/39] arm64: uaccess: Don't bother eliding access_ok checks in __{get, put}_user Alex Shi
2018-03-09 9:06 ` [PATCH 10/39] arm64: futex: Mask __user pointers prior to dereference Alex Shi
2018-03-09 9:06 ` [PATCH 11/39] drivers/firmware: Expose psci_get_version through psci_ops structure Alex Shi
2018-03-09 9:06 ` [PATCH 12/39] arm64: Move post_ttbr_update_workaround to C code Alex Shi
2018-03-09 9:06 ` [PATCH 13/39] arm64: Add skeleton to harden the branch predictor against aliasing attacks Alex Shi
2018-03-09 9:06 ` [PATCH 14/39] arm64: Move BP hardening to check_and_switch_context Alex Shi
2018-03-09 9:06 ` [PATCH 15/39] arm64: KVM: Use per-CPU vector when BP hardening is enabled Alex Shi
2018-03-09 9:06 ` [PATCH 16/39] arm64: entry: Apply BP hardening for high-priority synchronous exceptions Alex Shi
2018-03-09 9:07 ` [PATCH 17/39] arm64: entry: Apply BP hardening for suspicious interrupts from EL0 Alex Shi
2018-03-09 9:07 ` [PATCH 18/39] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Alex Shi
2018-03-09 9:07 ` [PATCH 19/39] arm64: prefetch: add alternative pattern for CPUs without a prefetcher Alex Shi
2018-03-09 9:07 ` [PATCH 20/39] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Alex Shi
2018-03-09 9:07 ` Alex Shi [this message]
2018-03-09 9:07 ` [PATCH 22/39] arm64: KVM: Increment PC after handling an SMC trap Alex Shi
2018-03-09 9:07 ` [PATCH 23/39] arm/arm64: KVM: Consolidate the PSCI include files Alex Shi
2018-03-09 9:07 ` [PATCH 24/39] arm/arm64: KVM: Add PSCI_VERSION helper Alex Shi
2018-03-09 9:07 ` [PATCH 25/39] arm/arm64: KVM: Add smccc accessors to PSCI code Alex Shi
2018-03-09 9:07 ` [PATCH 26/39] arm/arm64: KVM: Implement PSCI 1.0 support Alex Shi
2018-03-09 9:07 ` [PATCH 27/39] ARM: 8478/2: arm/arm64: add arm-smccc Alex Shi
2018-03-09 9:07 ` [PATCH 28/39] ARM: 8479/2: add implementation for arm-smccc Alex Shi
2018-03-09 9:07 ` [PATCH 29/39] ARM: 8480/2: arm64: " Alex Shi
2018-03-09 9:07 ` [PATCH 30/39] ARM: 8481/2: drivers: psci: replace psci firmware calls Alex Shi
2018-03-09 9:07 ` [PATCH 31/39] arm/arm64: KVM: Advertise SMCCC v1.1 Alex Shi
2018-03-09 9:07 ` [PATCH 32/39] arm/arm64: KVM: Turn kvm_psci_version into a static inline Alex Shi
2018-03-09 9:07 ` [PATCH 33/39] arm64: KVM: Report SMCCC_ARCH_WORKAROUND_1 BP hardening support Alex Shi
2018-03-09 9:07 ` [PATCH 34/39] arm64: KVM: Add SMCCC_ARCH_WORKAROUND_1 fast handling Alex Shi
2018-03-09 9:07 ` [PATCH 35/39] firmware/psci: Expose PSCI conduit Alex Shi
2018-03-09 9:07 ` [PATCH 36/39] firmware/psci: Expose SMCCC version through psci_ops Alex Shi
2018-03-09 9:07 ` [PATCH 37/39] arm/arm64: smccc: Make function identifiers an unsigned quantity Alex Shi
2018-03-09 9:07 ` [PATCH 38/39] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive Alex Shi
2018-03-09 9:07 ` [PATCH 39/39] arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support Alex Shi
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