[PATCH 0/8] Refresh Marvell BG2CD SoC support

[PATCH 0/8] Refresh Marvell BG2CD SoC support

[Alexander Monakov]

Hello,

I'd like to submit a few simple fixes and updates for Marvell BG2CD support
in mainline and Devicetree board file for the device I'm testing this on.

I've also submitted a one-bit fix for USB timeout issues on this board [1]
and a couple of one-line fixes for poor boot-time kernel warnings [2], [3].

Of course with support for DMA and audio/video subsystem entirely missing,
mainline is not very useful on this SoC right now, but nevertheless it may
be a good playground for the curious.

Thanks.

[1] https://patchwork.kernel.org/patch/10257793/
[2] https://patchwork.kernel.org/patch/10252479/
[3] http://patchwork.ozlabs.org/patch/883146/

Alexander Monakov (8):
  ARM: berlin: extend BG2CD Kconfig entry
  ARM: dts: berlin2cd: fix local timer interrupt flags
  ARM: dts: berlin2cd: move PMU node from soc to root
  ARM: dts: berlin2cd: add ADC/thermal sensor node
  ARM: dts: berlin2cd: add remaining Cortex-A9 nodes
  ARM: dts: berlin2cd: add remaining nodes to apb subtrees
  ARM: dts: berlin2cd: add a label for the CPU node
  ARM: dts: berlin2cd: add Valve Steam Link board

 arch/arm/boot/dts/Makefile                      |   1 +
 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts |  80 ++++++++++++++
 arch/arm/boot/dts/berlin2cd.dtsi                | 134 ++++++++++++++++++++++--
 arch/arm/mach-berlin/Kconfig                    |   7 +-
 4 files changed, 214 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts

-- 
2.11.0

[PATCH 1/8] ARM: berlin: extend BG2CD Kconfig entry

[Alexander Monakov]

BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect
pertinent errata, the SCU and the global timer, and allow use of the
local timer on uniprocessor kernels.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/mach-berlin/Kconfig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 63ab1d368625..d07ed4cd5fd7 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -23,9 +23,14 @@ config MACH_BERLIN_BG2
 
 config MACH_BERLIN_BG2CD
 	bool "Marvell Armada 1500-mini (BG2CD)"
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_775420
+	select ARM_GLOBAL_TIMER
 	select CACHE_L2X0
-	select HAVE_ARM_TWD if SMP
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD
 	select PINCTRL_BERLIN_BG2CD
+	select PL310_ERRATA_769419
 
 config MACH_BERLIN_BG2Q
 	bool "Marvell Armada 1500 Pro (BG2-Q)"
-- 
2.11.0

[PATCH 1/8] ARM: berlin: extend BG2CD Kconfig entry

[Jisheng Zhang]

On Sun, 11 Mar 2018 19:00:01 +0300 Alexander Monakov wrote:

> BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect
> pertinent errata, the SCU and the global timer, and allow use of the
> local timer on uniprocessor kernels.
> 
> Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
> ---
>  arch/arm/mach-berlin/Kconfig | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
> index 63ab1d368625..d07ed4cd5fd7 100644
> --- a/arch/arm/mach-berlin/Kconfig
> +++ b/arch/arm/mach-berlin/Kconfig
> @@ -23,9 +23,14 @@ config MACH_BERLIN_BG2
>  
>  config MACH_BERLIN_BG2CD
>  	bool "Marvell Armada 1500-mini (BG2CD)"
> +	select ARM_ERRATA_754322
> +	select ARM_ERRATA_775420
> +	select ARM_GLOBAL_TIMER
>  	select CACHE_L2X0
> -	select HAVE_ARM_TWD if SMP
> +	select HAVE_ARM_SCU
> +	select HAVE_ARM_TWD
>  	select PINCTRL_BERLIN_BG2CD
> +	select PL310_ERRATA_769419

IIRC, BG2CD doesn't need this

>  
>  config MACH_BERLIN_BG2Q
>  	bool "Marvell Armada 1500 Pro (BG2-Q)"

[PATCH 1/8] ARM: berlin: extend BG2CD Kconfig entry

[Alexander Monakov]

On Wed, 14 Mar 2018, Jisheng Zhang wrote:

> > +	select PL310_ERRATA_769419
> 
> IIRC, BG2CD doesn't need this

Indeed, PL310 in BG2CD has revision r3p2 and so is not affected. My mistake.
I think I was confused because the kernel tests affected revision ranges for
other PL310 errata, but not this one (and always applies the workaround).

Thank you! Will drop this line when reposting the patch.

Alexander

[PATCHv2 1/8] ARM: berlin: extend BG2CD Kconfig entry

[Alexander Monakov]

BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect
pertinent errata, the SCU and the global timer, and allow use of the
local timer on uniprocessor kernels.

PL310 L2 cache controller has revision r3p2; no errata to select.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
v2: address feedback from Jisheng:
* do not autoselect any PL310 errata

 arch/arm/mach-berlin/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 63ab1d368625..3d719cf645e3 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -23,8 +23,12 @@ config MACH_BERLIN_BG2
 
 config MACH_BERLIN_BG2CD
 	bool "Marvell Armada 1500-mini (BG2CD)"
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_775420
+	select ARM_GLOBAL_TIMER
 	select CACHE_L2X0
-	select HAVE_ARM_TWD if SMP
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD
 	select PINCTRL_BERLIN_BG2CD
 
 config MACH_BERLIN_BG2Q
-- 
2.11.0

[PATCH 2/8] ARM: dts: berlin2cd: fix local timer interrupt flags

[Alexander Monakov]

Use the correct trigger type for Cortex-A9. This was fixed for several
other SoCs since the kernel started issuing a boot-time warning.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 501c59d97eae..8c8bf3194f34 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -118,7 +118,7 @@
 		local-timer at ad0600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
 			clocks = <&chip_clk CLKID_TWD>;
 		};
 
-- 
2.11.0

[PATCH 3/8] ARM: dts: berlin2cd: move PMU node from soc to root

[Alexander Monakov]

Cortex-A9 PMU has no associated memory ranges and "make dtbs W=1" warns
about missing reg or ranges property. To avoid the warning, move the PMU
node out of soc subtree to the root.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 8c8bf3194f34..572e99ce5940 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -73,6 +73,12 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	refclk: oscillator {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -87,11 +93,6 @@
 
 		ranges = <0 0xf7000000 0x1000000>;
 
-		pmu {
-			compatible = "arm,cortex-a9-pmu";
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
 		sdhci0: sdhci at ab0000 {
 			compatible = "mrvl,pxav3-mmc";
 			reg = <0xab0000 0x200>;
-- 
2.11.0

[PATCH 4/8] ARM: dts: berlin2cd: add ADC/thermal sensor node

[Alexander Monakov]

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 572e99ce5940..c6929f84b201 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -480,6 +480,12 @@
 				sys_pinctrl: pin-controller {
 					compatible = "marvell,berlin2cd-system-pinctrl";
 				};
+
+				adc: adc {
+					compatible = "marvell,berlin2-adc";
+					interrupts = <12>, <14>;
+					interrupt-names = "adc", "tsen";
+				};
 			};
 
 			sic: interrupt-controller at e000 {
-- 
2.11.0

[PATCH 5/8] ARM: dts: berlin2cd: add remaining Cortex-A9 nodes

[Alexander Monakov]

This adds DT nodes for the Cortex-A9 MPCore SCU, local watchdog and
most importantly the global timer.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index c6929f84b201..7da6da3f0222 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -109,6 +109,11 @@
 			cache-level = <2>;
 		};
 
+		snoop-control-unit at ad0000 {
+			compatible = "arm,cortex-a9-scu";
+			reg = <0xad0000 0x100>;
+		};
+
 		gic: interrupt-controller at ad1000 {
 			compatible = "arm,cortex-a9-gic";
 			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@@ -116,6 +121,13 @@
 			#interrupt-cells = <3>;
 		};
 
+		global-timer at ad0200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0xad0200 0x20>;
+			interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
+			clocks = <&chip_clk CLKID_TWD>;
+		};
+
 		local-timer at ad0600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xad0600 0x20>;
@@ -123,6 +135,13 @@
 			clocks = <&chip_clk CLKID_TWD>;
 		};
 
+		local-wdt at ad0620 {
+			compatible = "arm,cortex-a9-twd-wdt";
+			reg = <0xad0620 0x20>;
+			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
+			clocks = <&chip_clk CLKID_TWD>;
+		};
+
 		usb_phy0: usb-phy at b74000 {
 			compatible = "marvell,berlin2cd-usb-phy";
 			reg = <0xb74000 0x128>;
-- 
2.11.0

[PATCH 6/8] ARM: dts: berlin2cd: add remaining nodes to apb subtrees

[Alexander Monakov]

This adds most of the remaining Designware IP cores under APB trees in
the interest of documenting assignment of interrupts and memory ranges.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 94 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 7da6da3f0222..c1da34c3c32c 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -274,6 +274,60 @@
 				};
 			};
 
+			i2c0: i2c at 1400 {
+				compatible = "snps,designware-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x1400 0x100>;
+				interrupts = <16>;
+				clocks = <&chip_clk CLKID_CFG>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 1800 {
+				compatible = "snps,designware-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x1800 0x100>;
+				interrupts = <17>;
+				clocks = <&chip_clk CLKID_CFG>;
+				status = "disabled";
+			};
+
+			spi0: spi at 1c00 {
+				compatible = "snps,dw-apb-ssi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x1c00 0x100>;
+				interrupts = <4>;
+				clocks = <&chip_clk CLKID_CFG>;
+				status = "disabled";
+			};
+
+			wdt4: watchdog at 2000 {
+				compatible = "snps,dw-wdt";
+				reg = <0x2000 0x100>;
+				clocks = <&chip_clk CLKID_CFG>;
+				interrupts = <5>;
+				status = "disabled";
+			};
+
+			wdt5: watchdog at 2400 {
+				compatible = "snps,dw-wdt";
+				reg = <0x2400 0x100>;
+				clocks = <&chip_clk CLKID_CFG>;
+				interrupts = <6>;
+				status = "disabled";
+			};
+
+			wdt6: watchdog at 2800 {
+				compatible = "snps,dw-wdt";
+				reg = <0x2800 0x100>;
+				clocks = <&chip_clk CLKID_CFG>;
+				interrupts = <7>;
+				status = "disabled";
+			};
+
 			timer0: timer at 2c00 {
 				compatible = "snps,dw-apb-timer";
 				reg = <0x2c00 0x14>;
@@ -455,6 +509,36 @@
 				};
 			};
 
+			spi1: spi at 6000 {
+				compatible = "snps,dw-apb-ssi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x6000 0x100>;
+				clocks = <&refclk>;
+				interrupts = <5>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 7000 {
+				compatible = "snps,designware-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x7000 0x100>;
+				interrupts = <6>;
+				clocks = <&refclk>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 8000 {
+				compatible = "snps,designware-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x8000 0x100>;
+				interrupts = <7>;
+				clocks = <&refclk>;
+				status = "disabled";
+			};
+
 			sm_gpio0: gpio at c000 {
 				compatible = "snps,dw-apb-gpio";
 				reg = <0xc000 0x400>;
@@ -492,6 +576,16 @@
 				status = "disabled";
 			};
 
+			uart2: serial at b000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xb000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <10>;
+				clocks = <&refclk>;
+				status = "disabled";
+			};
+
 			sysctrl: system-controller at d000 {
 				compatible = "simple-mfd", "syscon";
 				reg = <0xd000 0x100>;
-- 
2.11.0

[PATCH 7/8] ARM: dts: berlin2cd: add a label for the CPU node

[Alexander Monakov]

This is useful if the board file needs to reference it.

Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
 arch/arm/boot/dts/berlin2cd.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index c1da34c3c32c..92811d61e669 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -57,7 +57,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu: cpu at 0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			next-level-cache = <&l2>;
-- 
2.11.0

[PATCH 8/8] ARM: dts: berlin2cd: add Valve Steam Link board

[Alexander Monakov]

Valve Steam Link is a consumer device built around the Marvell BG2CD SoC.
This board file enables the UART, USB and Ethernet interfaces as well as
internal I2C and SDIO, and adds SoC voltage regulator and board-specific
GPIO restart method info.

Cc: Sam Lantinga <saml@valvesoftware.com>
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
At this point, major missing user-facing features are audio/video and
power management (cpufreq, cpuidle, and/or suspend).

It's easy to wire up the Vivante 3D graphics core, but without scanout
it's not useful.

For avoidance of doubt, I am not affiliated with Valve.

 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts | 80 +++++++++++++++++++++++++
 2 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..e52fa7168dd8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
 dtb-$(CONFIG_ARCH_BERLIN) += \
 	berlin2-sony-nsz-gs7.dtb \
 	berlin2cd-google-chromecast.dtb \
+	berlin2cd-valve-steamlink.dtb \
 	berlin2q-marvell-dmp.dtb
 dtb-$(CONFIG_ARCH_BRCMSTB) += \
 	bcm7445-bcm97445svmb.dtb
diff --git a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
new file mode 100644
index 000000000000..3161ada6eb34
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+/dts-v1/;
+
+#include "berlin2cd.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Valve Steam Link";
+	compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin";
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
+		active-delay = <100>;
+		inactive-delay = <10>;
+		wait-delay = <100>;
+		priority = <200>;
+	};
+};
+
+&cpu {
+	cpu-supply = <&vcpu>;
+	operating-points = <
+		/* kHz    uV */
+		1000000 1325000
+	>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	/* There are two regulators on the board. One is accessible via I2C,
+	 * with buck1 providing SoC power (set up by bootloader to 1.325V or
+	 * less depending on leakage value in OTP), and buck2 likely used for
+	 * DRAM (providing 1.35V). The other regulator on the opposite side
+	 * of the board is probably supplying SDIO and NAND fixed voltages. */
+	regulator at 19 {
+		compatible = "marvell,88pg868";
+		reg = <0x19>;
+
+		vcpu: buck1 {
+			regulator-boot-on;
+			regulator-always-on;
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1325000>;
+		};
+	};
+};
+
+/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */
+&sdhci0 {
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	/* RX/TX are routed to TP50/TP51 on the board. */
+	status = "okay";
+};
+
+/* The SoC is connected to on-board USB hub that in turn has one downstream
+ * port wired to the on-board Steam Controller wireless receiver chip. */
+&usb_phy1 { status = "okay"; };
+
+&usb1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&eth1 { status = "okay"; };
-- 
2.11.0

[PATCH 8/8] ARM: dts: berlin2cd: add Valve Steam Link board

[Jisheng Zhang]

Hi,

On Sun, 11 Mar 2018 19:00:08 +0300 Alexander Monakov wrote:

> Valve Steam Link is a consumer device built around the Marvell BG2CD SoC.
> This board file enables the UART, USB and Ethernet interfaces as well as
> internal I2C and SDIO, and adds SoC voltage regulator and board-specific
> GPIO restart method info.
> 
> Cc: Sam Lantinga <saml@valvesoftware.com>
> Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
> ---
> At this point, major missing user-facing features are audio/video and
> power management (cpufreq, cpuidle, and/or suspend).
> 
> It's easy to wire up the Vivante 3D graphics core, but without scanout
> it's not useful.
> 
> For avoidance of doubt, I am not affiliated with Valve.
> 
>  arch/arm/boot/dts/Makefile                      |  1 +
>  arch/arm/boot/dts/berlin2cd-valve-steamlink.dts | 80 +++++++++++++++++++++++++
>  2 files changed, 81 insertions(+)
>  create mode 100644 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d0381e9caf21..e52fa7168dd8 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
>  dtb-$(CONFIG_ARCH_BERLIN) += \
>  	berlin2-sony-nsz-gs7.dtb \
>  	berlin2cd-google-chromecast.dtb \
> +	berlin2cd-valve-steamlink.dtb \
>  	berlin2q-marvell-dmp.dtb
>  dtb-$(CONFIG_ARCH_BRCMSTB) += \
>  	bcm7445-bcm97445svmb.dtb
> diff --git a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
> new file mode 100644
> index 000000000000..3161ada6eb34
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
> @@ -0,0 +1,80 @@
> +/*
> + * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)

Mind to license it under GPL2 or X11?

Other source usually tag as:
// SPDX-License-Identifier: (GPL-2.0 OR X11)

And the tag is put into the first line, could we keep the style?

> + */
> +/dts-v1/;
> +
> +#include "berlin2cd.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "Valve Steam Link";
> +	compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin";
> +
> +	memory at 0 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x20000000>; /* 512 MB */
> +	};
> +
> +	gpio-restart {
> +		compatible = "gpio-restart";
> +		gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
> +		active-delay = <100>;
> +		inactive-delay = <10>;
> +		wait-delay = <100>;
> +		priority = <200>;
> +	};
> +};
> +
> +&cpu {
> +	cpu-supply = <&vcpu>;
> +	operating-points = <
> +		/* kHz    uV */
> +		1000000 1325000
> +	>;
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	/* There are two regulators on the board. One is accessible via I2C,
> +	 * with buck1 providing SoC power (set up by bootloader to 1.325V or
> +	 * less depending on leakage value in OTP), and buck2 likely used for
> +	 * DRAM (providing 1.35V). The other regulator on the opposite side
> +	 * of the board is probably supplying SDIO and NAND fixed voltages. */
> +	regulator at 19 {
> +		compatible = "marvell,88pg868";
> +		reg = <0x19>;
> +
> +		vcpu: buck1 {
> +			regulator-boot-on;
> +			regulator-always-on;
> +			regulator-min-microvolt = <1000000>;
> +			regulator-max-microvolt = <1325000>;
> +		};
> +	};
> +};
> +
> +/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */
> +&sdhci0 {
> +	keep-power-in-suspend;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	/* RX/TX are routed to TP50/TP51 on the board. */
> +	status = "okay";
> +};
> +
> +/* The SoC is connected to on-board USB hub that in turn has one downstream
> + * port wired to the on-board Steam Controller wireless receiver chip. */
> +&usb_phy1 { status = "okay"; };
> +
> +&usb1 {
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +&eth1 { status = "okay"; };

[PATCH 8/8] ARM: dts: berlin2cd: add Valve Steam Link board

[Alexander Monakov]

On Wed, 14 Mar 2018, Jisheng Zhang wrote:

> > +/*
> > + * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> 
> Mind to license it under GPL2 or X11?

MIT is the same as X11 but without the references to the X Consortium that
do not make sense in the kernel context: please see [1] and [2]. The MIT
license is present under LICENSES/preferred in the kernel tree, but not the
X11 license.

The berlin2cd.dtsi file first says "the X11 license", but then the actual
license text appearing in the file is the MIT license.

[1] https://spdx.org/licenses/MIT.html
[2] https://spdx.org/licenses/X11.html

> Other source usually tag as:
> // SPDX-License-Identifier: (GPL-2.0 OR X11)
> 
> And the tag is put into the first line, could we keep the style?

Right. With the clarification regarding X11/MIT above, I'll change to

// SPDX-License-Identifier: GPL-2.0 OR MIT
// Copyright 2018 Alexander Monakov <amonakov@gmail.com>

Is that okay?

Thanks.
Alexander

[PATCH 8/8] ARM: dts: berlin2cd: add Valve Steam Link board

[Jisheng Zhang]

On Wed, 14 Mar 2018 10:22:11 +0300 Alexander Monakov wrote:

> On Wed, 14 Mar 2018, Jisheng Zhang wrote:
> 
> > > +/*
> > > + * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
> > > + *
> > > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)  
> > 
> > Mind to license it under GPL2 or X11?  
> 
> MIT is the same as X11 but without the references to the X Consortium that
> do not make sense in the kernel context: please see [1] and [2]. The MIT
> license is present under LICENSES/preferred in the kernel tree, but not the
> X11 license.

Understood.

> 
> The berlin2cd.dtsi file first says "the X11 license", but then the actual
> license text appearing in the file is the MIT license.

Yes, I'll send patches to add SPDX tags to all berlin SoC dtsi and s/X11/MIT.

Thanks for pointing this out.

> 
> [1] https://spdx.org/licenses/MIT.html
> [2] https://spdx.org/licenses/X11.html
> 
> > Other source usually tag as:
> > // SPDX-License-Identifier: (GPL-2.0 OR X11)
> > 
> > And the tag is put into the first line, could we keep the style?  
> 
> Right. With the clarification regarding X11/MIT above, I'll change to
> 
> // SPDX-License-Identifier: GPL-2.0 OR MIT
> // Copyright 2018 Alexander Monakov <amonakov@gmail.com>
> 
> Is that okay?

Yes, it's OK.

[PATCH 8/8] ARM: dts: berlin2cd: add Valve Steam Link board

[Jisheng Zhang]

On Wed, 14 Mar 2018 15:43:23 +0800 Jisheng Zhang wrote:

> On Wed, 14 Mar 2018 10:22:11 +0300 Alexander Monakov wrote:
> 

<snip>

> > > Other source usually tag as:
> > > // SPDX-License-Identifier: (GPL-2.0 OR X11)
> > > 
> > > And the tag is put into the first line, could we keep the style?    
> > 
> > Right. With the clarification regarding X11/MIT above, I'll change to
> > 
> > // SPDX-License-Identifier: GPL-2.0 OR MIT
> > // Copyright 2018 Alexander Monakov <amonakov@gmail.com>
> > 
> > Is that okay?  
> 
> Yes, it's OK.

I think something as the following is fine:


// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
 */

[PATCHv2 8/8] ARM: dts: berlin2cd: add Valve Steam Link board

[Alexander Monakov]

Valve Steam Link is a consumer device built around the Marvell BG2CD SoC.
This board file enables the UART, USB and Ethernet interfaces as well as
internal I2C and SDIO, and adds SoC voltage regulator and board-specific
GPIO restart method info.

Cc: Sam Lantinga <saml@valvesoftware.com>
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
---
v2: address feedback from Jisheng:
* adjust styling of opening comment with SPDX license info

 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts | 79 +++++++++++++++++++++++++
 2 files changed, 80 insertions(+)
 create mode 100644 arch/arm/boot/dts/berlin2cd-valve-steamlink.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ade7a38543dc..82153e323030 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
 dtb-$(CONFIG_ARCH_BERLIN) += \
 	berlin2-sony-nsz-gs7.dtb \
 	berlin2cd-google-chromecast.dtb \
+	berlin2cd-valve-steamlink.dtb \
 	berlin2q-marvell-dmp.dtb
 dtb-$(CONFIG_ARCH_BRCMSTB) += \
 	bcm7445-bcm97445svmb.dtb
diff --git a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
new file mode 100644
index 000000000000..79ac842ae461
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
+ */
+/dts-v1/;
+
+#include "berlin2cd.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Valve Steam Link";
+	compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin";
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
+		active-delay = <100>;
+		inactive-delay = <10>;
+		wait-delay = <100>;
+		priority = <200>;
+	};
+};
+
+&cpu {
+	cpu-supply = <&vcpu>;
+	operating-points = <
+		/* kHz    uV */
+		1000000 1325000
+	>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	/* There are two regulators on the board. One is accessible via I2C,
+	 * with buck1 providing SoC power (set up by bootloader to 1.325V or
+	 * less depending on leakage value in OTP), and buck2 likely used for
+	 * DRAM (providing 1.35V). The other regulator on the opposite side
+	 * of the board is probably supplying SDIO and NAND fixed voltages. */
+	regulator at 19 {
+		compatible = "marvell,88pg868";
+		reg = <0x19>;
+
+		vcpu: buck1 {
+			regulator-boot-on;
+			regulator-always-on;
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1325000>;
+		};
+	};
+};
+
+/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */
+&sdhci0 {
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	/* RX/TX are routed to TP50/TP51 on the board. */
+	status = "okay";
+};
+
+/* The SoC is connected to on-board USB hub that in turn has one downstream
+ * port wired to the on-board Steam Controller wireless receiver chip. */
+&usb_phy1 { status = "okay"; };
+
+&usb1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&eth1 { status = "okay"; };
-- 
2.11.0