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From: robh@kernel.org (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 05/27] dts: bindings: Document device tree binding for CATU
Date: Tue, 1 May 2018 08:10:57 -0500	[thread overview]
Message-ID: <20180501131057.GA15706@rob-hp-laptop> (raw)
In-Reply-To: <1525165857-11096-6-git-send-email-suzuki.poulose@arm.com>

On Tue, May 01, 2018 at 10:10:35AM +0100, Suzuki K Poulose wrote:
> Document CATU device-tree bindings. CATU augments the TMC-ETR
> by providing an improved Scatter Gather mechanism for streaming
> trace data to non-contiguous system RAM pages.
> 
> Cc: devicetree at vger.kernel.org
> Cc: frowand.list at gmail.com
> Cc: Rob Herring <robh@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  .../devicetree/bindings/arm/coresight.txt          | 52 ++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 15ac8e8..cdd84d0 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -39,6 +39,8 @@ its hardware characteristcs.
>  
>  		- System Trace Macrocell:
>  			"arm,coresight-stm", "arm,primecell"; [1]
> +		- Coresight Address Translation Unit (CATU)
> +			"arm, coresight-catu", "arm,primecell";

spurious space               ^

>  
>  	* reg: physical base address and length of the register
>  	  set(s) of the component.
> @@ -86,6 +88,9 @@ its hardware characteristcs.
>  	* arm,buffer-size: size of contiguous buffer space for TMC ETR
>  	 (embedded trace router)
>  
> +* Optional property for CATU :
> +	* interrupts : Exactly one SPI may be listed for reporting the address
> +	  error

Somewhere you need to define the ports for the CATU.

>  
>  Example:
>  
> @@ -118,6 +123,35 @@ Example:
>  		};
>  	};
>  
> +	etr at 20070000 {
> +		compatible = "arm,coresight-tmc", "arm,primecell";
> +		reg = <0 0x20070000 0 0x1000>;
> +
> +		clocks = <&oscclk6a>;
> +		clock-names = "apb_pclk";
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* input port */
> +			port at 0 {
> +				reg =  <0>;
> +				etr_in_port: endpoint {
> +					slave-mode;
> +					remote-endpoint = <&replicator2_out_port0>;
> +				};
> +			};
> +
> +			/* CATU link represented by output port */
> +			port at 1 {
> +				reg = <0>;

While common in the Coresight bindings, having unit-address and reg not 
match is an error. Mathieu and I discussed this a bit as dtc now warns 
on these.

Either reg should be 1 here, or 'ports' needs to be split into input and 
output ports. My preference would be the former, but Mathieu objected to 
this not reflecting the the h/w numbering.

Rob

  reply	other threads:[~2018-05-01 13:10 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-01  9:10 [PATCH v2 00/27] coresight: TMC ETR backend support for perf Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 01/27] coresight: ETM: Add support for ARM Cortex-A73 Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 02/27] coresight: Cleanup device subtype struct Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 03/27] coresight: Add helper device type Suzuki K Poulose
2018-05-03 17:00   ` Mathieu Poirier
2018-05-05  9:56     ` Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 04/27] coresight: Introduce support for Coresight Addrss Translation Unit Suzuki K Poulose
2018-05-03 17:31   ` Mathieu Poirier
2018-05-03 20:25     ` Mathieu Poirier
2018-05-05 10:03       ` Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 05/27] dts: bindings: Document device tree binding for CATU Suzuki K Poulose
2018-05-01 13:10   ` Rob Herring [this message]
2018-05-03 17:42     ` Mathieu Poirier
2018-05-08 15:40       ` Suzuki K Poulose
2018-05-11 16:05         ` Rob Herring
2018-05-14 14:42           ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 06/27] coresight: tmc etr: Disallow perf mode temporarily Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 07/27] coresight: tmc: Hide trace buffer handling for file read Suzuki K Poulose
2018-05-03 19:50   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 08/27] coresight: tmc-etr: Do not clean trace buffer Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 09/27] coresight: Add helper for inserting synchronization packets Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 10/27] dts: bindings: Restrict coresight tmc-etr scatter-gather mode Suzuki K Poulose
2018-05-01 13:13   ` Rob Herring
2018-05-03 20:32     ` Mathieu Poirier
2018-05-04 22:56       ` Rob Herring
2018-05-08 15:48         ` Suzuki K Poulose
2018-05-08 17:34           ` Rob Herring
2018-05-01  9:10 ` [PATCH v2 11/27] dts: juno: Add scatter-gather support for all revisions Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 12/27] coresight: tmc-etr: Allow commandline option to override SG use Suzuki K Poulose
2018-05-03 20:40   ` Mathieu Poirier
2018-05-08 15:49     ` Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 13/27] coresight: Add generic TMC sg table framework Suzuki K Poulose
2018-05-04 17:35   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 14/27] coresight: Add support for TMC ETR SG unit Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 15/27] coresight: tmc-etr: Make SG table circular Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 16/27] coresight: tmc-etr: Add transparent buffer management Suzuki K Poulose
2018-05-07 17:20   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 17/27] coresight: etr: Add support for save restore buffers Suzuki K Poulose
2018-05-07 17:48   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 18/27] coresight: catu: Add support for scatter gather tables Suzuki K Poulose
2018-05-07 20:25   ` Mathieu Poirier
2018-05-08 15:56     ` Suzuki K Poulose
2018-05-08 16:13       ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 19/27] coresight: catu: Plug in CATU as a backend for ETR buffer Suzuki K Poulose
2018-05-07 22:02   ` Mathieu Poirier
2018-05-08 16:21     ` Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 20/27] coresight: tmc: Add configuration support for trace buffer size Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 21/27] coresight: Convert driver messages to dev_dbg Suzuki K Poulose
2018-05-02  3:55   ` Kim Phillips
2018-05-02  8:25     ` Robert Walker
2018-05-02 13:52     ` Robin Murphy
2018-05-10 13:36       ` Suzuki K Poulose
2018-05-07 22:28   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 22/27] coresight: tmc-etr: Track if the device is coherent Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 23/27] coresight: tmc-etr: Handle driver mode specific ETR buffers Suzuki K Poulose
2018-05-08 17:18   ` Mathieu Poirier
2018-05-08 21:51     ` Suzuki K Poulose
2018-05-09 17:12       ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 24/27] coresight: tmc-etr: Relax collection of trace from sysfs mode Suzuki K Poulose
2018-05-07 22:54   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 25/27] coresight: etr_buf: Add helper for padding an area of trace data Suzuki K Poulose
2018-05-08 17:34   ` Mathieu Poirier
2018-05-01  9:10 ` [PATCH v2 26/27] coresight: perf: Remove reset_buffer call back for sinks Suzuki K Poulose
2018-05-08 19:42   ` Mathieu Poirier
2018-05-11 16:35     ` Suzuki K Poulose
2018-05-01  9:10 ` [PATCH v2 27/27] coresight: etm-perf: Add support for ETR backend Suzuki K Poulose
2018-05-08 22:04   ` Mathieu Poirier

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