* Delivery Status Notification (Failure) [not found] ` <5af57fea.1c69fb81.885f0.2377.GMRIR@mx.google.com> @ 2018-05-11 11:37 ` Pintu Kumar 2018-05-11 12:39 ` Russell King - ARM Linux 0 siblings, 1 reply; 10+ messages in thread From: Pintu Kumar @ 2018-05-11 11:37 UTC (permalink / raw) To: linux-arm-kernel Hi, I need one help. I am using i.MX7 Sabre board with kernel version 4.1.15 Let's say I am interested in GPIO number: 21 I wanted to set CPU affinity for particular GPIO->IRQ number, so I tried the below steps: root at 10:~# echo 21 > /sys/class/gpio/export root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge root at 10:~# cat /proc/interrupts | grep 21 47: 0 0 gpio-mxc 21 Edge gpiolib root at 10:~# cat /sys/class/gpio/gpio21/direction in root at 10:~# cat /proc/irq/47/smp_affinity 3 root at 10:~# echo 2 > /proc/irq/47/smp_affinity -bash: echo: write error: Input/output error But I get input/output error. When I debug further, found that irq_can_set_affinity is returning 0: [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, irq_data.chip: a81b7e48, irq_set_affinity: (null) [ 0.000000] write_irq_affinity: FAIL I also tried first setting /proc/irq/default_smp_affinity to 2 (from 3). This change is working, but the smp_affinity setting for the new IRQ is not working. When I try to set smp_affinity for mmc0, then it works. # cat /proc/interrupts | grep mmc 295: 55 0 GPCV2 22 Edge mmc0 296: 0 0 GPCV2 23 Edge mmc1 297: 52 0 GPCV2 24 Edge mmc2 root at 10:~# echo 2 > /proc/irq/295/smp_affinity root at 10:~# So, I wanted to know what are the conditions for which setting smp_affinity for an IRQ will work ? Is there any way by which I can set CPU affinity to a GPIO -> IRQ ? Whether, irq_set_affinity_hint() will work in this case ? Thanks, Pintu ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-11 11:37 ` Delivery Status Notification (Failure) Pintu Kumar @ 2018-05-11 12:39 ` Russell King - ARM Linux 2018-05-11 13:04 ` Lucas Stach 0 siblings, 1 reply; 10+ messages in thread From: Russell King - ARM Linux @ 2018-05-11 12:39 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: > Hi, > > I need one help. > I am using i.MX7 Sabre board with kernel version 4.1.15 > > Let's say I am interested in GPIO number: 21 > I wanted to set CPU affinity for particular GPIO->IRQ number, so I > tried the below steps: > root at 10:~# echo 21 > /sys/class/gpio/export > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge > root at 10:~# cat /proc/interrupts | grep 21 > 47: 0 0 gpio-mxc 21 Edge gpiolib > root at 10:~# cat /sys/class/gpio/gpio21/direction > in > root at 10:~# cat /proc/irq/47/smp_affinity > 3 > root at 10:~# echo 2 > /proc/irq/47/smp_affinity > -bash: echo: write error: Input/output error > > But I get input/output error. > When I debug further, found that irq_can_set_affinity is returning 0: > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, > irq_data.chip: a81b7e48, irq_set_affinity: (null) > [ 0.000000] write_irq_affinity: FAIL > > I also tried first setting /proc/irq/default_smp_affinity to 2 (from 3). > This change is working, but the smp_affinity setting for the new IRQ > is not working. > > When I try to set smp_affinity for mmc0, then it works. > # cat /proc/interrupts | grep mmc > 295: 55 0 GPCV2 22 Edge mmc0 > 296: 0 0 GPCV2 23 Edge mmc1 > 297: 52 0 GPCV2 24 Edge mmc2 > > root at 10:~# echo 2 > /proc/irq/295/smp_affinity > root at 10:~# > > > So, I wanted to know what are the conditions for which setting > smp_affinity for an IRQ will work ? > > Is there any way by which I can set CPU affinity to a GPIO -> IRQ ? > Whether, irq_set_affinity_hint() will work in this case ? IRQ affinity is only supported where interrupts are _directly_ wired to the GIC. It's the GIC which does the interrupt steering to the CPU cores. Interrupts on downstream interrupt controllers (such as GPCV2) have no ability to be directed independently to other CPUs - the only possible way to change the mapping is to move _all_ interrupts on that controller, and any downstream chained interrupts at GIC level. Hence why Interrupt 295 has no irq_set_affinity function: there is no way for the interrupt controller itself to change the affinity of the input interrupt. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up According to speedtest.net: 8.21Mbps down 510kbps up ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-11 12:39 ` Russell King - ARM Linux @ 2018-05-11 13:04 ` Lucas Stach 2018-05-11 14:37 ` Pintu Kumar 0 siblings, 1 reply; 10+ messages in thread From: Lucas Stach @ 2018-05-11 13:04 UTC (permalink / raw) To: linux-arm-kernel Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - ARM Linux: > On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: > > Hi, > > > > I need one help. > > I am using i.MX7 Sabre board with kernel version 4.1.15 > > > > Let's say I am interested in GPIO number: 21 > > I wanted to set CPU affinity for particular GPIO->IRQ number, so I > > tried the below steps: > > root at 10:~# echo 21 > /sys/class/gpio/export > > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge > > root at 10:~# cat /proc/interrupts | grep 21 > > 47: 0 0 gpio-mxc 21 Edge gpiolib > > root at 10:~# cat /sys/class/gpio/gpio21/direction > > in > > root at 10:~# cat /proc/irq/47/smp_affinity > > 3 > > root at 10:~# echo 2 > /proc/irq/47/smp_affinity > > -bash: echo: write error: Input/output error > > > > But I get input/output error. > > When I debug further, found that irq_can_set_affinity is returning 0: > > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, > > irq_data.chip: a81b7e48, irq_set_affinity: (null) > > [ 0.000000] write_irq_affinity: FAIL > > > > I also tried first setting /proc/irq/default_smp_affinity to 2 (from 3). > > This change is working, but the smp_affinity setting for the new IRQ > > is not working. > > > > When I try to set smp_affinity for mmc0, then it works. > > # cat /proc/interrupts | grep mmc > > 295: 55 0 GPCV2 22 Edge mmc0 > > 296: 0 0 GPCV2 23 Edge mmc1 > > 297: 52 0 GPCV2 24 Edge mmc2 > > > > root at 10:~# echo 2 > /proc/irq/295/smp_affinity > > root at 10:~# > > > > > > So, I wanted to know what are the conditions for which setting > > smp_affinity for an IRQ will work ? > > > > Is there any way by which I can set CPU affinity to a GPIO -> IRQ ? > > Whether, irq_set_affinity_hint() will work in this case ? > > IRQ affinity is only supported where interrupts are _directly_ wired to > the GIC. It's the GIC which does the interrupt steering to the CPU > cores. > > Interrupts on downstream interrupt controllers (such as GPCV2) have no > ability to be directed independently to other CPUs - the only possible > way to change the mapping is to move _all_ interrupts on that controller, > and any downstream chained interrupts at GIC level. > > Hence why Interrupt 295 has no irq_set_affinity function: there is no way > for the interrupt controller itself to change the affinity of the input > interrupt. The GPCv2 though is a secondary IRQ controller which has a 1:1 mapping of its input IRQs to the upstream GIC IRQ lines. Affinity can thus be handled by forwarding the request to the GIC by irq_chip_set_affinity_parent(). As this is handled correctly in the upstream kernel since the first commit introducing support for the GPCv2, it seems the issue is only present in some downstream kernel. Regards, Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-11 13:04 ` Lucas Stach @ 2018-05-11 14:37 ` Pintu Kumar 2018-05-14 12:12 ` Pintu Kumar 0 siblings, 1 reply; 10+ messages in thread From: Pintu Kumar @ 2018-05-11 14:37 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.de> wrote: > Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - ARM Linux: >> On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: >> > Hi, >> > >> > I need one help. >> > I am using i.MX7 Sabre board with kernel version 4.1.15 >> > >> > Let's say I am interested in GPIO number: 21 >> > I wanted to set CPU affinity for particular GPIO->IRQ number, so I >> > tried the below steps: >> > root at 10:~# echo 21 > /sys/class/gpio/export >> > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge >> > root at 10:~# cat /proc/interrupts | grep 21 >> > 47: 0 0 gpio-mxc 21 Edge gpiolib >> > root at 10:~# cat /sys/class/gpio/gpio21/direction >> > in >> > root at 10:~# cat /proc/irq/47/smp_affinity >> > 3 >> > root at 10:~# echo 2 > /proc/irq/47/smp_affinity >> > -bash: echo: write error: Input/output error >> > >> > But I get input/output error. >> > When I debug further, found that irq_can_set_affinity is returning 0: >> > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, >> > irq_data.chip: a81b7e48, irq_set_affinity: (null) >> > [ 0.000000] write_irq_affinity: FAIL >> > >> > I also tried first setting /proc/irq/default_smp_affinity to 2 (from 3). >> > This change is working, but the smp_affinity setting for the new IRQ >> > is not working. >> > >> > When I try to set smp_affinity for mmc0, then it works. >> > # cat /proc/interrupts | grep mmc >> > 295: 55 0 GPCV2 22 Edge mmc0 >> > 296: 0 0 GPCV2 23 Edge mmc1 >> > 297: 52 0 GPCV2 24 Edge mmc2 >> > >> > root at 10:~# echo 2 > /proc/irq/295/smp_affinity >> > root at 10:~# >> > >> > >> > So, I wanted to know what are the conditions for which setting >> > smp_affinity for an IRQ will work ? >> > >> > Is there any way by which I can set CPU affinity to a GPIO -> IRQ ? >> > Whether, irq_set_affinity_hint() will work in this case ? >> >> IRQ affinity is only supported where interrupts are _directly_ wired to >> the GIC. It's the GIC which does the interrupt steering to the CPU >> cores. >> >> Interrupts on downstream interrupt controllers (such as GPCV2) have no >> ability to be directed independently to other CPUs - the only possible >> way to change the mapping is to move _all_ interrupts on that controller, >> and any downstream chained interrupts at GIC level. >> >> Hence why Interrupt 295 has no irq_set_affinity function: there is no way >> for the interrupt controller itself to change the affinity of the input >> interrupt. > > The GPCv2 though is a secondary IRQ controller which has a 1:1 mapping > of its input IRQs to the upstream GIC IRQ lines. Affinity can thus be > handled by forwarding the request to the GIC by > irq_chip_set_affinity_parent(). > > As this is handled correctly in the upstream kernel since the first > commit introducing support for the GPCv2, it seems the issue is only > present in some downstream kernel. > OK. Thanks so much for your reply. I saw some of the drivers using irq_set_affinity_hint() to force the IRQ affinity to a particular CPU. This is the sample: { cpumask_clear(mask); cpumask_set_cpu(cpu, mask); irq_set_affinity_hint(irq, mask); } Whether this logic will work for a particular GPIO pin ? > Regards, > Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-11 14:37 ` Pintu Kumar @ 2018-05-14 12:12 ` Pintu Kumar 2018-05-14 13:11 ` Lucas Stach 0 siblings, 1 reply; 10+ messages in thread From: Pintu Kumar @ 2018-05-14 12:12 UTC (permalink / raw) To: linux-arm-kernel Hi, Is there any work around possible to set IRQ affinity for some GPIO interrupt ? How to avoid CPU0 to receive the current GPIO interrupt ? How do we assign GPIO interrupts to any CPU other than CPU0 ? Is it possible to isolate CPU0 for a sometime, from my GPIO driver so that GPIO interrupt can be served by another CPU ? Need your inputs to decide whether it is still possible to set affinity for GPIO interrupt, or its impossible ? Thanks, Pintu On Fri, May 11, 2018 at 8:07 PM, Pintu Kumar <pintu.ping@gmail.com> wrote: > On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.de> wrote: >> Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - ARM Linux: >>> On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: >>> > Hi, >>> > >>> > I need one help. >>> > I am using i.MX7 Sabre board with kernel version 4.1.15 >>> > >>> > Let's say I am interested in GPIO number: 21 >>> > I wanted to set CPU affinity for particular GPIO->IRQ number, so I >>> > tried the below steps: >>> > root at 10:~# echo 21 > /sys/class/gpio/export >>> > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge >>> > root at 10:~# cat /proc/interrupts | grep 21 >>> > 47: 0 0 gpio-mxc 21 Edge gpiolib >>> > root at 10:~# cat /sys/class/gpio/gpio21/direction >>> > in >>> > root at 10:~# cat /proc/irq/47/smp_affinity >>> > 3 >>> > root at 10:~# echo 2 > /proc/irq/47/smp_affinity >>> > -bash: echo: write error: Input/output error >>> > >>> > But I get input/output error. >>> > When I debug further, found that irq_can_set_affinity is returning 0: >>> > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, >>> > irq_data.chip: a81b7e48, irq_set_affinity: (null) >>> > [ 0.000000] write_irq_affinity: FAIL >>> > >>> > I also tried first setting /proc/irq/default_smp_affinity to 2 (from 3). >>> > This change is working, but the smp_affinity setting for the new IRQ >>> > is not working. >>> > >>> > When I try to set smp_affinity for mmc0, then it works. >>> > # cat /proc/interrupts | grep mmc >>> > 295: 55 0 GPCV2 22 Edge mmc0 >>> > 296: 0 0 GPCV2 23 Edge mmc1 >>> > 297: 52 0 GPCV2 24 Edge mmc2 >>> > >>> > root at 10:~# echo 2 > /proc/irq/295/smp_affinity >>> > root at 10:~# >>> > >>> > >>> > So, I wanted to know what are the conditions for which setting >>> > smp_affinity for an IRQ will work ? >>> > >>> > Is there any way by which I can set CPU affinity to a GPIO -> IRQ ? >>> > Whether, irq_set_affinity_hint() will work in this case ? >>> >>> IRQ affinity is only supported where interrupts are _directly_ wired to >>> the GIC. It's the GIC which does the interrupt steering to the CPU >>> cores. >>> >>> Interrupts on downstream interrupt controllers (such as GPCV2) have no >>> ability to be directed independently to other CPUs - the only possible >>> way to change the mapping is to move _all_ interrupts on that controller, >>> and any downstream chained interrupts at GIC level. >>> >>> Hence why Interrupt 295 has no irq_set_affinity function: there is no way >>> for the interrupt controller itself to change the affinity of the input >>> interrupt. >> >> The GPCv2 though is a secondary IRQ controller which has a 1:1 mapping >> of its input IRQs to the upstream GIC IRQ lines. Affinity can thus be >> handled by forwarding the request to the GIC by >> irq_chip_set_affinity_parent(). >> >> As this is handled correctly in the upstream kernel since the first >> commit introducing support for the GPCv2, it seems the issue is only >> present in some downstream kernel. >> > > OK. Thanks so much for your reply. > > I saw some of the drivers using irq_set_affinity_hint() to force the > IRQ affinity to a particular CPU. > This is the sample: > { > cpumask_clear(mask); > cpumask_set_cpu(cpu, mask); > irq_set_affinity_hint(irq, mask); > } > > Whether this logic will work for a particular GPIO pin ? > > >> Regards, >> Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-14 12:12 ` Pintu Kumar @ 2018-05-14 13:11 ` Lucas Stach 2018-05-14 14:28 ` Pintu Kumar 0 siblings, 1 reply; 10+ messages in thread From: Lucas Stach @ 2018-05-14 13:11 UTC (permalink / raw) To: linux-arm-kernel Am Montag, den 14.05.2018, 17:42 +0530 schrieb Pintu Kumar: > Hi, > > Is there any work around possible to set IRQ affinity for some GPIO > interrupt ? > How to avoid CPU0 to receive the current GPIO interrupt ? > How do we assign GPIO interrupts to any CPU other than CPU0 ? > Is it possible to isolate CPU0 for a sometime, from my GPIO driver so > that GPIO interrupt can be served by another CPU ? > > Need your inputs to decide whether it is still possible to set > affinity for GPIO interrupt, or its impossible ? This is not possible. The GPIO IRQs are aggregated into one GPC/GIC IRQ line per GPIO bank, so it is not possible to change affinity of a single GPIO interrupt to another CPU. Best we could do is change the affinity of the whole bank, but given the limited usefulness of something like that, nobody bothered to implement such a thing. Regards, Lucas > > > On Fri, May 11, 2018 at 8:07 PM, Pintu Kumar <pintu.ping@gmail.com> > wrote: > > On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.d > > e> wrote: > > > Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - > > > ARM Linux: > > > > On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: > > > > > Hi, > > > > > > > > > > I need one help. > > > > > I am using i.MX7 Sabre board with kernel version 4.1.15 > > > > > > > > > > Let's say I am interested in GPIO number: 21 > > > > > I wanted to set CPU affinity for particular GPIO->IRQ number, > > > > > so I > > > > > tried the below steps: > > > > > root at 10:~# echo 21 > /sys/class/gpio/export > > > > > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge > > > > > root at 10:~# cat /proc/interrupts | grep 21 > > > > > ? 47: 0 0 gpio-mxc 21 Edge gpiolib > > > > > root at 10:~# cat /sys/class/gpio/gpio21/direction > > > > > in > > > > > root at 10:~# cat /proc/irq/47/smp_affinity > > > > > 3 > > > > > root at 10:~# echo 2 > /proc/irq/47/smp_affinity > > > > > -bash: echo: write error: Input/output error > > > > > > > > > > But I get input/output error. > > > > > When I debug further, found that irq_can_set_affinity is > > > > > returning 0: > > > > > [????0.000000] genirq: irq_can_set_affinity (0): balance: 1, > > > > > irq_data.chip: a81b7e48, irq_set_affinity:???(null) > > > > > [????0.000000] write_irq_affinity: FAIL > > > > > > > > > > I also tried first setting /proc/irq/default_smp_affinity to > > > > > 2 (from 3). > > > > > This change is working, but the smp_affinity setting for the > > > > > new IRQ > > > > > is not working. > > > > > > > > > > When I try to set smp_affinity for mmc0, then it works. > > > > > # cat /proc/interrupts | grep mmc > > > > > 295:?????????55??????????0?????GPCV2??22 Edge??????mmc0 > > > > > 296:??????????0??????????0?????GPCV2??23 Edge??????mmc1 > > > > > 297:?????????52??????????0?????GPCV2??24 Edge??????mmc2 > > > > > > > > > > root at 10:~# echo 2 > /proc/irq/295/smp_affinity > > > > > root at 10:~# > > > > > > > > > > > > > > > So, I wanted to know what are the conditions for which > > > > > setting > > > > > smp_affinity for an IRQ will work ? > > > > > > > > > > Is there any way by which I can set CPU affinity to a GPIO -> > > > > > IRQ ? > > > > > Whether, irq_set_affinity_hint() will work in this case ? > > > > > > > > IRQ affinity is only supported where interrupts are _directly_ > > > > wired to > > > > the GIC.??It's the GIC which does the interrupt steering to the > > > > CPU > > > > cores. > > > > > > > > Interrupts on downstream interrupt controllers (such as GPCV2) > > > > have no > > > > ability to be directed independently to other CPUs - the only > > > > possible > > > > way to change the mapping is to move _all_ interrupts on that > > > > controller, > > > > and any downstream chained interrupts at GIC level. > > > > > > > > Hence why Interrupt 295 has no irq_set_affinity function: there > > > > is no way > > > > for the interrupt controller itself to change the affinity of > > > > the input > > > > interrupt. > > > > > > The GPCv2 though is a secondary IRQ controller which has a 1:1 > > > mapping > > > of its input IRQs to the upstream GIC IRQ lines. Affinity can > > > thus be > > > handled by forwarding the request to the GIC by > > > irq_chip_set_affinity_parent(). > > > > > > As this is handled correctly in the upstream kernel since the > > > first > > > commit introducing support for the GPCv2, it seems the issue is > > > only > > > present in some downstream kernel. > > > > > > > OK. Thanks so much for your reply. > > > > I saw some of the drivers using irq_set_affinity_hint() to force > > the > > IRQ affinity to a particular CPU. > > This is the sample: > > { > > cpumask_clear(mask); > > cpumask_set_cpu(cpu, mask); > > irq_set_affinity_hint(irq, mask); > > } > > > > Whether this logic will work for a particular GPIO pin ? > > > > > > > Regards, > > > Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-14 13:11 ` Lucas Stach @ 2018-05-14 14:28 ` Pintu Kumar 2018-05-17 13:28 ` Pintu Kumar 0 siblings, 1 reply; 10+ messages in thread From: Pintu Kumar @ 2018-05-14 14:28 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 14, 2018 at 6:41 PM, Lucas Stach <l.stach@pengutronix.de> wrote: > Am Montag, den 14.05.2018, 17:42 +0530 schrieb Pintu Kumar: >> Hi, >> >> Is there any work around possible to set IRQ affinity for some GPIO >> interrupt ? >> How to avoid CPU0 to receive the current GPIO interrupt ? >> How do we assign GPIO interrupts to any CPU other than CPU0 ? >> Is it possible to isolate CPU0 for a sometime, from my GPIO driver so >> that GPIO interrupt can be served by another CPU ? >> >> Need your inputs to decide whether it is still possible to set >> affinity for GPIO interrupt, or its impossible ? > > This is not possible. The GPIO IRQs are aggregated into one GPC/GIC IRQ > line per GPIO bank, so it is not possible to change affinity of a > single GPIO interrupt to another CPU. OK. Thanks for your confirmation. > Best we could do is change the > affinity of the whole bank, OK. How can we do this on the fly from my driver code. If you have any reference please let me know. This is required only for experimental purpose to prove the point to be mgmt. My idea is, from the driver, change the affinity of the whole bank. So, the GPIO interrupt can be delivered on to this specific CPU bank. Once I am done, I will revert back to the old bank. Please give me some hint on how to do this from my kernel module.... > but given the limited usefulness of > something like that, nobody bothered to implement such a thing. > > Regards, > Lucas > >> >> >> On Fri, May 11, 2018 at 8:07 PM, Pintu Kumar <pintu.ping@gmail.com> >> wrote: >> > On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.d >> > e> wrote: >> > > Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - >> > > ARM Linux: >> > > > On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: >> > > > > Hi, >> > > > > >> > > > > I need one help. >> > > > > I am using i.MX7 Sabre board with kernel version 4.1.15 >> > > > > >> > > > > Let's say I am interested in GPIO number: 21 >> > > > > I wanted to set CPU affinity for particular GPIO->IRQ number, >> > > > > so I >> > > > > tried the below steps: >> > > > > root at 10:~# echo 21 > /sys/class/gpio/export >> > > > > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge >> > > > > root at 10:~# cat /proc/interrupts | grep 21 >> > > > > 47: 0 0 gpio-mxc 21 Edge gpiolib >> > > > > root at 10:~# cat /sys/class/gpio/gpio21/direction >> > > > > in >> > > > > root at 10:~# cat /proc/irq/47/smp_affinity >> > > > > 3 >> > > > > root at 10:~# echo 2 > /proc/irq/47/smp_affinity >> > > > > -bash: echo: write error: Input/output error >> > > > > >> > > > > But I get input/output error. >> > > > > When I debug further, found that irq_can_set_affinity is >> > > > > returning 0: >> > > > > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, >> > > > > irq_data.chip: a81b7e48, irq_set_affinity: (null) >> > > > > [ 0.000000] write_irq_affinity: FAIL >> > > > > >> > > > > I also tried first setting /proc/irq/default_smp_affinity to >> > > > > 2 (from 3). >> > > > > This change is working, but the smp_affinity setting for the >> > > > > new IRQ >> > > > > is not working. >> > > > > >> > > > > When I try to set smp_affinity for mmc0, then it works. >> > > > > # cat /proc/interrupts | grep mmc >> > > > > 295: 55 0 GPCV2 22 Edge mmc0 >> > > > > 296: 0 0 GPCV2 23 Edge mmc1 >> > > > > 297: 52 0 GPCV2 24 Edge mmc2 >> > > > > >> > > > > root at 10:~# echo 2 > /proc/irq/295/smp_affinity >> > > > > root at 10:~# >> > > > > >> > > > > >> > > > > So, I wanted to know what are the conditions for which >> > > > > setting >> > > > > smp_affinity for an IRQ will work ? >> > > > > >> > > > > Is there any way by which I can set CPU affinity to a GPIO -> >> > > > > IRQ ? >> > > > > Whether, irq_set_affinity_hint() will work in this case ? >> > > > >> > > > IRQ affinity is only supported where interrupts are _directly_ >> > > > wired to >> > > > the GIC. It's the GIC which does the interrupt steering to the >> > > > CPU >> > > > cores. >> > > > >> > > > Interrupts on downstream interrupt controllers (such as GPCV2) >> > > > have no >> > > > ability to be directed independently to other CPUs - the only >> > > > possible >> > > > way to change the mapping is to move _all_ interrupts on that >> > > > controller, >> > > > and any downstream chained interrupts at GIC level. >> > > > >> > > > Hence why Interrupt 295 has no irq_set_affinity function: there >> > > > is no way >> > > > for the interrupt controller itself to change the affinity of >> > > > the input >> > > > interrupt. >> > > >> > > The GPCv2 though is a secondary IRQ controller which has a 1:1 >> > > mapping >> > > of its input IRQs to the upstream GIC IRQ lines. Affinity can >> > > thus be >> > > handled by forwarding the request to the GIC by >> > > irq_chip_set_affinity_parent(). >> > > >> > > As this is handled correctly in the upstream kernel since the >> > > first >> > > commit introducing support for the GPCv2, it seems the issue is >> > > only >> > > present in some downstream kernel. >> > > >> > >> > OK. Thanks so much for your reply. >> > >> > I saw some of the drivers using irq_set_affinity_hint() to force >> > the >> > IRQ affinity to a particular CPU. >> > This is the sample: >> > { >> > cpumask_clear(mask); >> > cpumask_set_cpu(cpu, mask); >> > irq_set_affinity_hint(irq, mask); >> > } >> > >> > Whether this logic will work for a particular GPIO pin ? >> > >> > >> > > Regards, >> > > Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-14 14:28 ` Pintu Kumar @ 2018-05-17 13:28 ` Pintu Kumar 2018-05-21 18:51 ` Pintu Kumar 0 siblings, 1 reply; 10+ messages in thread From: Pintu Kumar @ 2018-05-17 13:28 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 14, 2018 at 7:58 PM, Pintu Kumar <pintu.ping@gmail.com> wrote: > > On Mon, May 14, 2018 at 6:41 PM, Lucas Stach <l.stach@pengutronix.de> wrote: > > Am Montag, den 14.05.2018, 17:42 +0530 schrieb Pintu Kumar: > >> Hi, > >> > >> Is there any work around possible to set IRQ affinity for some GPIO > >> interrupt ? > >> How to avoid CPU0 to receive the current GPIO interrupt ? > >> How do we assign GPIO interrupts to any CPU other than CPU0 ? > >> Is it possible to isolate CPU0 for a sometime, from my GPIO driver so > >> that GPIO interrupt can be served by another CPU ? > >> > >> Need your inputs to decide whether it is still possible to set > >> affinity for GPIO interrupt, or its impossible ? > > > > This is not possible. The GPIO IRQs are aggregated into one GPC/GIC IRQ > > line per GPIO bank, so it is not possible to change affinity of a > > single GPIO interrupt to another CPU. > > OK. Thanks for your confirmation. > > > Best we could do is change the > > affinity of the whole bank, > Hi, I found that the driver is responsible for setting GPIO bank in i.MX7: https://elixir.bootlin.com/linux/v4.2/source/drivers/gpio/gpio-mxc.c However I still dont know how to set the cpumask for one of the GPIO Bank. >From this link, it seems it is possible to set affinity for a GPIO IRQ. https://community.nxp.com/thread/303144 But when I try it form my GPIO138 (GPIO5_IO10) it did not help. So, as you said, I wanted to change affinity for the whole GPIO bank and try it. Please give me some pointers. Thanks > OK. How can we do this on the fly from my driver code. > If you have any reference please let me know. > This is required only for experimental purpose to prove the point to be mgmt. > My idea is, from the driver, change the affinity of the whole bank. > So, the GPIO interrupt can be delivered on to this specific CPU bank. > Once I am done, I will revert back to the old bank. > Please give me some hint on how to do this from my kernel module.... > > > > but given the limited usefulness of > > something like that, nobody bothered to implement such a thing. > > > > Regards, > > Lucas > > > >> > >> > >> On Fri, May 11, 2018 at 8:07 PM, Pintu Kumar <pintu.ping@gmail.com> > >> wrote: > >> > On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.d > >> > e> wrote: > >> > > Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - > >> > > ARM Linux: > >> > > > On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: > >> > > > > Hi, > >> > > > > > >> > > > > I need one help. > >> > > > > I am using i.MX7 Sabre board with kernel version 4.1.15 > >> > > > > > >> > > > > Let's say I am interested in GPIO number: 21 > >> > > > > I wanted to set CPU affinity for particular GPIO->IRQ number, > >> > > > > so I > >> > > > > tried the below steps: > >> > > > > root at 10:~# echo 21 > /sys/class/gpio/export > >> > > > > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge > >> > > > > root at 10:~# cat /proc/interrupts | grep 21 > >> > > > > 47: 0 0 gpio-mxc 21 Edge gpiolib > >> > > > > root at 10:~# cat /sys/class/gpio/gpio21/direction > >> > > > > in > >> > > > > root at 10:~# cat /proc/irq/47/smp_affinity > >> > > > > 3 > >> > > > > root at 10:~# echo 2 > /proc/irq/47/smp_affinity > >> > > > > -bash: echo: write error: Input/output error > >> > > > > > >> > > > > But I get input/output error. > >> > > > > When I debug further, found that irq_can_set_affinity is > >> > > > > returning 0: > >> > > > > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, > >> > > > > irq_data.chip: a81b7e48, irq_set_affinity: (null) > >> > > > > [ 0.000000] write_irq_affinity: FAIL > >> > > > > > >> > > > > I also tried first setting /proc/irq/default_smp_affinity to > >> > > > > 2 (from 3). > >> > > > > This change is working, but the smp_affinity setting for the > >> > > > > new IRQ > >> > > > > is not working. > >> > > > > > >> > > > > When I try to set smp_affinity for mmc0, then it works. > >> > > > > # cat /proc/interrupts | grep mmc > >> > > > > 295: 55 0 GPCV2 22 Edge mmc0 > >> > > > > 296: 0 0 GPCV2 23 Edge mmc1 > >> > > > > 297: 52 0 GPCV2 24 Edge mmc2 > >> > > > > > >> > > > > root at 10:~# echo 2 > /proc/irq/295/smp_affinity > >> > > > > root at 10:~# > >> > > > > > >> > > > > > >> > > > > So, I wanted to know what are the conditions for which > >> > > > > setting > >> > > > > smp_affinity for an IRQ will work ? > >> > > > > > >> > > > > Is there any way by which I can set CPU affinity to a GPIO -> > >> > > > > IRQ ? > >> > > > > Whether, irq_set_affinity_hint() will work in this case ? > >> > > > > >> > > > IRQ affinity is only supported where interrupts are _directly_ > >> > > > wired to > >> > > > the GIC. It's the GIC which does the interrupt steering to the > >> > > > CPU > >> > > > cores. > >> > > > > >> > > > Interrupts on downstream interrupt controllers (such as GPCV2) > >> > > > have no > >> > > > ability to be directed independently to other CPUs - the only > >> > > > possible > >> > > > way to change the mapping is to move _all_ interrupts on that > >> > > > controller, > >> > > > and any downstream chained interrupts at GIC level. > >> > > > > >> > > > Hence why Interrupt 295 has no irq_set_affinity function: there > >> > > > is no way > >> > > > for the interrupt controller itself to change the affinity of > >> > > > the input > >> > > > interrupt. > >> > > > >> > > The GPCv2 though is a secondary IRQ controller which has a 1:1 > >> > > mapping > >> > > of its input IRQs to the upstream GIC IRQ lines. Affinity can > >> > > thus be > >> > > handled by forwarding the request to the GIC by > >> > > irq_chip_set_affinity_parent(). > >> > > > >> > > As this is handled correctly in the upstream kernel since the > >> > > first > >> > > commit introducing support for the GPCv2, it seems the issue is > >> > > only > >> > > present in some downstream kernel. > >> > > > >> > > >> > OK. Thanks so much for your reply. > >> > > >> > I saw some of the drivers using irq_set_affinity_hint() to force > >> > the > >> > IRQ affinity to a particular CPU. > >> > This is the sample: > >> > { > >> > cpumask_clear(mask); > >> > cpumask_set_cpu(cpu, mask); > >> > irq_set_affinity_hint(irq, mask); > >> > } > >> > > >> > Whether this logic will work for a particular GPIO pin ? > >> > > > >> > > >> > > Regards, > >> > > Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
* Delivery Status Notification (Failure) 2018-05-17 13:28 ` Pintu Kumar @ 2018-05-21 18:51 ` Pintu Kumar 0 siblings, 0 replies; 10+ messages in thread From: Pintu Kumar @ 2018-05-21 18:51 UTC (permalink / raw) To: linux-arm-kernel Dear Lucas, Can you give me some pointers on how to set affinity for entire GPIO Bank. Currently I am exploring drivers/gpio/gpio-mxc.c to find out how the GPIO banks are set up. I also found that affinity can be set using: desc->irq_data.affinity, may be by using cpumask_copy(...). But still I am not familiar with this. So, I need your help. Thank You! Regards, Pintu On Thu, May 17, 2018 at 6:58 PM, Pintu Kumar <pintu.ping@gmail.com> wrote: > On Mon, May 14, 2018 at 7:58 PM, Pintu Kumar <pintu.ping@gmail.com> wrote: >> >> On Mon, May 14, 2018 at 6:41 PM, Lucas Stach <l.stach@pengutronix.de> wrote: >> > Am Montag, den 14.05.2018, 17:42 +0530 schrieb Pintu Kumar: >> >> Hi, >> >> >> >> Is there any work around possible to set IRQ affinity for some GPIO >> >> interrupt ? >> >> How to avoid CPU0 to receive the current GPIO interrupt ? >> >> How do we assign GPIO interrupts to any CPU other than CPU0 ? >> >> Is it possible to isolate CPU0 for a sometime, from my GPIO driver so >> >> that GPIO interrupt can be served by another CPU ? >> >> >> >> Need your inputs to decide whether it is still possible to set >> >> affinity for GPIO interrupt, or its impossible ? >> > >> > This is not possible. The GPIO IRQs are aggregated into one GPC/GIC IRQ >> > line per GPIO bank, so it is not possible to change affinity of a >> > single GPIO interrupt to another CPU. >> >> OK. Thanks for your confirmation. >> >> > Best we could do is change the >> > affinity of the whole bank, >> > > Hi, > > I found that the driver is responsible for setting GPIO bank in i.MX7: > https://elixir.bootlin.com/linux/v4.2/source/drivers/gpio/gpio-mxc.c > > However I still dont know how to set the cpumask for one of the GPIO Bank. > > From this link, it seems it is possible to set affinity for a GPIO IRQ. > https://community.nxp.com/thread/303144 > > But when I try it form my GPIO138 (GPIO5_IO10) it did not help. > > So, as you said, I wanted to change affinity for the whole GPIO bank and try it. > Please give me some pointers. > > Thanks > > >> OK. How can we do this on the fly from my driver code. >> If you have any reference please let me know. >> This is required only for experimental purpose to prove the point to be mgmt. >> My idea is, from the driver, change the affinity of the whole bank. >> So, the GPIO interrupt can be delivered on to this specific CPU bank. >> Once I am done, I will revert back to the old bank. >> Please give me some hint on how to do this from my kernel module.... >> >> >> > but given the limited usefulness of >> > something like that, nobody bothered to implement such a thing. >> > >> > Regards, >> > Lucas >> > >> >> >> >> >> >> On Fri, May 11, 2018 at 8:07 PM, Pintu Kumar <pintu.ping@gmail.com> >> >> wrote: >> >> > On Fri, May 11, 2018 at 6:34 PM, Lucas Stach <l.stach@pengutronix.d >> >> > e> wrote: >> >> > > Am Freitag, den 11.05.2018, 13:39 +0100 schrieb Russell King - >> >> > > ARM Linux: >> >> > > > On Fri, May 11, 2018 at 05:07:37PM +0530, Pintu Kumar wrote: >> >> > > > > Hi, >> >> > > > > >> >> > > > > I need one help. >> >> > > > > I am using i.MX7 Sabre board with kernel version 4.1.15 >> >> > > > > >> >> > > > > Let's say I am interested in GPIO number: 21 >> >> > > > > I wanted to set CPU affinity for particular GPIO->IRQ number, >> >> > > > > so I >> >> > > > > tried the below steps: >> >> > > > > root at 10:~# echo 21 > /sys/class/gpio/export >> >> > > > > root at 10:~# echo "rising" > /sys/class/gpio/gpio21/edge >> >> > > > > root at 10:~# cat /proc/interrupts | grep 21 >> >> > > > > 47: 0 0 gpio-mxc 21 Edge gpiolib >> >> > > > > root at 10:~# cat /sys/class/gpio/gpio21/direction >> >> > > > > in >> >> > > > > root at 10:~# cat /proc/irq/47/smp_affinity >> >> > > > > 3 >> >> > > > > root at 10:~# echo 2 > /proc/irq/47/smp_affinity >> >> > > > > -bash: echo: write error: Input/output error >> >> > > > > >> >> > > > > But I get input/output error. >> >> > > > > When I debug further, found that irq_can_set_affinity is >> >> > > > > returning 0: >> >> > > > > [ 0.000000] genirq: irq_can_set_affinity (0): balance: 1, >> >> > > > > irq_data.chip: a81b7e48, irq_set_affinity: (null) >> >> > > > > [ 0.000000] write_irq_affinity: FAIL >> >> > > > > >> >> > > > > I also tried first setting /proc/irq/default_smp_affinity to >> >> > > > > 2 (from 3). >> >> > > > > This change is working, but the smp_affinity setting for the >> >> > > > > new IRQ >> >> > > > > is not working. >> >> > > > > >> >> > > > > When I try to set smp_affinity for mmc0, then it works. >> >> > > > > # cat /proc/interrupts | grep mmc >> >> > > > > 295: 55 0 GPCV2 22 Edge mmc0 >> >> > > > > 296: 0 0 GPCV2 23 Edge mmc1 >> >> > > > > 297: 52 0 GPCV2 24 Edge mmc2 >> >> > > > > >> >> > > > > root at 10:~# echo 2 > /proc/irq/295/smp_affinity >> >> > > > > root at 10:~# >> >> > > > > >> >> > > > > >> >> > > > > So, I wanted to know what are the conditions for which >> >> > > > > setting >> >> > > > > smp_affinity for an IRQ will work ? >> >> > > > > >> >> > > > > Is there any way by which I can set CPU affinity to a GPIO -> >> >> > > > > IRQ ? >> >> > > > > Whether, irq_set_affinity_hint() will work in this case ? >> >> > > > >> >> > > > IRQ affinity is only supported where interrupts are _directly_ >> >> > > > wired to >> >> > > > the GIC. It's the GIC which does the interrupt steering to the >> >> > > > CPU >> >> > > > cores. >> >> > > > >> >> > > > Interrupts on downstream interrupt controllers (such as GPCV2) >> >> > > > have no >> >> > > > ability to be directed independently to other CPUs - the only >> >> > > > possible >> >> > > > way to change the mapping is to move _all_ interrupts on that >> >> > > > controller, >> >> > > > and any downstream chained interrupts at GIC level. >> >> > > > >> >> > > > Hence why Interrupt 295 has no irq_set_affinity function: there >> >> > > > is no way >> >> > > > for the interrupt controller itself to change the affinity of >> >> > > > the input >> >> > > > interrupt. >> >> > > >> >> > > The GPCv2 though is a secondary IRQ controller which has a 1:1 >> >> > > mapping >> >> > > of its input IRQs to the upstream GIC IRQ lines. Affinity can >> >> > > thus be >> >> > > handled by forwarding the request to the GIC by >> >> > > irq_chip_set_affinity_parent(). >> >> > > >> >> > > As this is handled correctly in the upstream kernel since the >> >> > > first >> >> > > commit introducing support for the GPCv2, it seems the issue is >> >> > > only >> >> > > present in some downstream kernel. >> >> > > >> >> > >> >> > OK. Thanks so much for your reply. >> >> > >> >> > I saw some of the drivers using irq_set_affinity_hint() to force >> >> > the >> >> > IRQ affinity to a particular CPU. >> >> > This is the sample: >> >> > { >> >> > cpumask_clear(mask); >> >> > cpumask_set_cpu(cpu, mask); >> >> > irq_set_affinity_hint(irq, mask); >> >> > } >> >> > >> >> > Whether this logic will work for a particular GPIO pin ? >> >> > > > >> >> >> > >> >> > > Regards, >> >> > > Lucas ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <CAFJTrDsaq-NjLhcwHBuN1Q_zu-Q-yJkWLMUER1zVzc1=AFNM=Q@mail.gmail.com>]
[parent not found: <047d7b86e7727b700204ea828c1d@google.com>]
* Delivery Status Notification (Failure) [not found] ` <047d7b86e7727b700204ea828c1d@google.com> @ 2013-11-06 14:06 ` Matthew Minter 0 siblings, 0 replies; 10+ messages in thread From: Matthew Minter @ 2013-11-06 14:06 UTC (permalink / raw) To: linux-arm-kernel Hi Everyone, I am sorry for the exceedingly long delay before replying, I have had a number of unrelated problems which have prevented me from working on this issue. The version of u-boot which caused this issue was Marvell's Q2-2013 release. I used this with a 3.12 rc1 and a 3.12 rc3 kernel, both receiving the errors I have mentioned above. I have ensured my low level debugging configuration is correct, it is indeed mapped correctly to the new register range and I do not believe this to be the problem, particularly as it crashes well after the early printk has begun giving output. Unfortunately I cannot find the log file from the kernel at this stage as it appears to have been filled and overwritten, I however did look into this further and Marvell have (since when I raised the problem) given me a patched u-boot which is no longer causing the issue (the patch seems to be dated mid October 2013), unfortunately I cant post the change log of the patch but it does appear the problem was caused by a buggy u-boot release (or at least that it is fixed with the patched version). I have since tested the new version with kernels 3.12 rc3 to 3.12 rc6 and none of them have any issues with booting. Here is a full diff of the change I made to the device tree file (dont mind the bogus timestamps) --- arch/arm/boot/dts/armada-xp-gp.dts.old 2013-11-06 13:39:17.440000000 +0000 +++ arch/arm/boot/dts/armada-xp-gp.dts 2013-11-05 17:32:16.160001348 +0000 @@ -39,7 +39,7 @@ }; soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; I think the issue therefore may not be a kernel issue after all and should likely not be worried about. However on a related matter, I had thought the kernel was supposed to have some kind of detection for the register location using cp15? Why does the device tree describe the register address staticly if this is the case? Ultimately I think the specific errors I was getting (along with the exact error being variable dependant on seemingly random factors) made the specific errors a red herring and the problem was due to a faulty initialisation by the bootloader. However if there is any other information I can give or if anyone is interested I may be able to find out more. Best regards, Matthew On 6 November 2013 13:58, Mail Delivery Subsystem <mailer-daemon@googlemail.com> wrote: > Delivery to the following recipient failed permanently: > > linux-arm-kernel at lists.infradead.org > > Technical details of permanent failure: > Google tried to deliver your message, but it was rejected by the server for the recipient domain lists.infradead.org by merlin.infradead.org. [205.233.59.134]. > > The error that the other server returned was: > 550-Mailing lists do not accept HTML mail. See > 550 http://david.woodhou.se/email.html > > ----- Original message ----- > > X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; > d=1e100.net; s=20130820; > h=x-gm-message-state:mime-version:in-reply-to:references:date > :message-id:subject:from:to:content-type; > bh=7ZxkcjMOgG2fPbDIq0WtE/eu/1H9O3KEeGtX4g0cEwc=; > b=dxwtJYHC5DNmtLbRqHF3nOw7L6jPlkQeYBV0Lu3X+NUD50WrnLJq4LaaA3Xc8p9ZdE > iq9axkL33lyu7+YL41iDM+uyXrVXdGfSevUw7VKm3LemgC6aVUM8Cjv9LTJIanncySaJ > nlgy2K1dGUEfQffHqC3hoZp5RqCudW4JtRBGCEkkwcRZPxD4ygh09XGeJlXkciZ5xwou > 7bBwPY1TrEqsnbMvZNW59OS6NMjePvRi4NlSSG62w7p1sbes4NnTZrzCWYKNEg0JSmdc > jpkoy04IypB54+95FyGFZzUOu3V3XKeTC2AvU9I/o8imwCVxcaW8hwaQ25er+ETEgWU9 > DK9Q== > X-Gm-Message-State: ALoCoQmHzfdGMpqQ7DTvrzz4hpObpdipXgf2lGK+1cbRTSUyoaRE9sz7r32vzDU4Dsf3MuyWtioe7lnz0x3W8va3BaN2qtW/4g1vpApNOlp2FOxktOlZoZfYLfTcDRAkcCTofZ7ZrhLE > MIME-Version: 1.0 > X-Received: by 10.66.159.234 with SMTP id xf10mr3984291pab.139.1383746298406; > Wed, 06 Nov 2013 05:58:18 -0800 (PST) > Received: by 10.68.193.138 with HTTP; Wed, 6 Nov 2013 05:58:18 -0800 (PST) > In-Reply-To: <20131022181141.3f567273@skate> > References: <CAFJTrDtznkpwi76yyEKYvjuo+XV34ky9AOe8Qfa5wm-uHDJT6A@mail.gmail.com> > <20131021174339.GA27284@localhost> > <20131021184219.GA24520@titan.lakedaemon.net> > <20131022152950.40171b36@skate> > <CAFJTrDtKw0ANh55Y6xQtFzGtvmZOJ-ZC6cFuKV62L0tmmhT3uA@mail.gmail.com> > <20131022181141.3f567273@skate> > Date: Wed, 6 Nov 2013 13:58:18 +0000 > Message-ID: <CAFJTrDsaq-NjLhcwHBuN1Q_zu-Q-yJkWLMUER1zVzc1=AFNM=Q@mail.gmail.com> > Subject: Re: Armada XP Internal registers > From: Matthew Minter <matthew_minter@xyratex.com> > To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, > Jason Cooper <jason@lakedaemon.net>, Ezequiel Garcia <ezequiel.garcia@free-electrons.com>, > linux-arm-kernel at lists.infradead.org > Content-Type: multipart/alternative; boundary=047d7b86e7729390ac04ea828a5b > > Hi Everyone, > > I am sorry for the exceedingly long delay before replying, I have had a > number of unrelated problems which have prevented me from working on this > issue. > > The version of u-boot which caused this issue was Marvell's Q2-2013 > release. I used this with a 3.12 rc1 and a 3.12 rc3 kernel, both receiving > the errors I have mentioned above. I have ensured my low level debugging > configuration is correct, it is indeed mapped correctly to the new register > range and I do not believe this to be the problem, particularly as it > crashes well after the early printk has begun giving output. > > Unfortunately I cannot find the log file from the kernel at this stage as > it appears to have been filled and overwritten, I however did look into > this further and Marvell have (since when I raised the problem) given me a > patched u-boot which is no longer causing the issue (the patch seems to be > dated mid October 2013), unfortunately I cant post the change log of the > patch but it does appear the problem was caused by a buggy u-boot release > (or at least that it is fixed with the patched version). I have since > tested the new version with kernels 3.12 rc3 to 3.12 rc6 and none of them > have any issues with booting. Here is a full diff of the change I made to > the device tree file (dont mind the bogus timestamps) > > --- arch/arm/boot/dts/armada-xp-gp.dts.old 2013-11-06 13:39:17.440000000 > +0000 > +++ arch/arm/boot/dts/armada-xp-gp.dts 2013-11-05 17:32:16.160001348 > +0000 > @@ -39,7 +39,7 @@ > }; > > soc { > - ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 > + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 > MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 > MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; > > I think the issue therefore may not be a kernel issue after all and should > likely not be worried about. However on a related matter, I had thought the > kernel was supposed to have some kind of detection for the register > > ----- Message truncated ----- > -- ------------------------------ For additional information including the registered office and the treatment of Xyratex confidential information please visit www.xyratex.com ------------------------------ ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-05-21 18:51 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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[not found] ` <5af57fea.1c69fb81.885f0.2377.GMRIR@mx.google.com>
2018-05-11 11:37 ` Delivery Status Notification (Failure) Pintu Kumar
2018-05-11 12:39 ` Russell King - ARM Linux
2018-05-11 13:04 ` Lucas Stach
2018-05-11 14:37 ` Pintu Kumar
2018-05-14 12:12 ` Pintu Kumar
2018-05-14 13:11 ` Lucas Stach
2018-05-14 14:28 ` Pintu Kumar
2018-05-17 13:28 ` Pintu Kumar
2018-05-21 18:51 ` Pintu Kumar
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[not found] ` <047d7b86e7727b700204ea828c1d@google.com>
2013-11-06 14:06 ` Matthew Minter
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