From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave.Martin@arm.com (Dave Martin) Date: Tue, 22 May 2018 15:11:46 +0100 Subject: [RFC PATCH v2] arm64: fault: Don't leak data in ESR context for user fault on kernel VA In-Reply-To: References: <20180419154833.27727-1-peter.maydell@linaro.org> <20180522133826.GE26955@arm.com> Message-ID: <20180522141146.GF13470@e103592.cambridge.arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, May 22, 2018 at 02:48:29PM +0100, Peter Maydell wrote: > On 22 May 2018 at 14:38, Will Deacon wrote: > > Hi Peter, > > > > Sorry for the delay in getting to this! Comments inline. > > > > On Thu, Apr 19, 2018 at 04:48:33PM +0100, Peter Maydell wrote: > > >> + /* > >> + * These bits provide only information about the > >> + * faulting instruction, which userspace knows already. > >> + * We explicitly clear bits which are architecturally > >> + * RES0 in case they are given meanings in future. > >> + */ > >> + if (esr & ESR_ELx_ISV) > >> + esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | > >> + ESR_ELx_ISV | ESR_ELx_SAS | > >> + ESR_ELx_SSE | ESR_ELx_SRT_MASK | > >> + ESR_ELx_SF | ESR_ELx_AR | ESR_ELx_CM | > >> + ESR_ELx_WNR; > > > > Reading through the ARM ARM, it seems to say that ISV is always 0 for > > faults reported in ESR_EL1, which implies we can drop ISV, SAS, SSE, SRT, > > SF and AR from this list and actually drop the conditional altogether. > > Mmm, I guess so, if we're guaranteed to only be working with ESRs > taken to EL1 (or we want to present userspace with an ESR that There is no direct interface between EL0 and EL2 with the stage2 translation enabled, so even if this data is available for a fault at EL2, we won't be signalling the fault via delivering a signal to EL0. > looks like that regardless of what EL we took it to). I'll respin > without the conditional. Sounds fair. It might have been me that suggested this list of fields in the first place: I'd not completely understood the ISV behaviour previously, it seems. Cheers ---Dave