From mboxrd@z Thu Jan 1 00:00:00 1970 From: miquel.raynal@bootlin.com (Miquel Raynal) Date: Thu, 5 Jul 2018 14:40:08 +0200 Subject: [PATCH v4 11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller In-Reply-To: <20180705124011.7661-1-miquel.raynal@bootlin.com> References: <20180705124011.7661-1-miquel.raynal@bootlin.com> Message-ID: <20180705124011.7661-12-miquel.raynal@bootlin.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Describe the System Error Interrupt (SEI) controller. It aggregates two types of interrupts, wired and MSIs from respectively the AP and the CPs, into a single SPI interrupt. Suggested-by: Haim Boot Signed-off-by: Miquel Raynal --- .../bindings/interrupt-controller/marvell,sei.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt new file mode 100644 index 000000000000..9aee3820f1a8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt @@ -0,0 +1,39 @@ +Marvell SEI (System Error Interrupt) Controller +----------------------------------------------- + +Marvell SEI (System Error Interrupt) controller is an interrupt +aggregator. It receives interrupts from several sources and aggregates +them to a single interrupt line (an SPI) on the parent interrupt +controller. + +This interrupt controller can handle up to 64 SEIs, a set comes from the +AP and is wired while a second set comes from the CPs by the mean of +MSIs. Each 'domain' is represented as a subnode. + +Required properties: + +- compatible: should be "marvell,armada-8k-sei". +- reg: SEI registers location and length. +- interrupts: identifies the parent IRQ that will be triggered. +- marvell,sei-ranges: two ranges, the first one describe wired + interrupts coming from the AP, the second one + non-wired interrupts (MSI) from the CPs. +- #interrupt-cells: number of cells to define an SEI wired interrupt + coming from the AP, should be 1. The cell is the IRQ + number. +- interrupt-controller: identifies the node as an interrupt controller + (AP only). +- msi-controller: identifies the node as an MSI controller (CPs only). + +Example: + + sei: interrupt-controller at 3f0200 { + compatible = "marvell,armada-8k-sei"; + reg = <0x3f0200 0x40>; + interrupts = ; + marvell,sei-ap-ranges = <0 21>; + marvell,sei-cp-ranges = <21 43>; + #interrupt-cells = <1>; + interrupt-controller; + msi-controller; + }; -- 2.14.1