* [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions
@ 2018-09-07 19:41 Corentin Labbe
2018-09-07 19:41 ` [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be Corentin Labbe
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw)
To: linux-arm-kernel
Hello
This patchset adds a new set of functions which are open-coded in lot of
place.
Basicly the pattern is always the same, "read, modify a bit, write"
some driver already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b)
The first patch rename some powerpc funtions which already use the same name (xxxbits32)
but with only bigendian values.
The second patch adds the header.
The third patch is an ugly try to implement a coccinelle semantic patch to
find all place where xxxbits function could be used.
Probably this spatch could be better written and I didnt found an easy way to add the "linux/setbits" header.
The two last patch are example of convertion of two drivers.
Thoses patchs give an example of the reduction of code won by using xxxbits32.
This patchset is tested with the ahci_sunxi and dwmac-sun8i drivers.
Regards
Corentin Labbe (5):
powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be
include: add
setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in
linux/setbits.h
coccinelle: add xxxsetbitsXX converting spatch
net: ethernet: stmmac: use xxxsetbits32
ata: ahci_sunxi: use xxxsetbits32 functions
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h | 5 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c | 28 +-
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 +-
arch/powerpc/platforms/82xx/ep8248e.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +-
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c | 10 +-
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 4 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +-
arch/powerpc/platforms/8xx/adder875.c | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +-
arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-
arch/powerpc/platforms/embedded6xx/wii.c | 10 +-
arch/powerpc/sysdev/cpm1.c | 26 +-
arch/powerpc/sysdev/cpm2.c | 16 +-
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +-
arch/powerpc/sysdev/fsl_lbc.c | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 8 +-
arch/powerpc/sysdev/fsl_pmc.c | 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74 ++--
arch/powerpc/sysdev/fsl_rio.c | 4 +-
arch/powerpc/sysdev/fsl_rmu.c | 8 +-
arch/powerpc/sysdev/mpic_timer.c | 12 +-
drivers/ata/ahci_sunxi.c | 51 +--
.../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 54 +--
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 55 +--
.../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 21 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 51 +--
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 13 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 42 +-
drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 11 +-
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 17 +-
.../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 30 +-
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 69 +---
.../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 11 +-
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 7 +-
include/linux/setbits.h | 55 +++
scripts/coccinelle/misc/setbits.cocci | 423 +++++++++++++++++++++
56 files changed, 776 insertions(+), 489 deletions(-)
create mode 100644 include/linux/setbits.h
create mode 100644 scripts/coccinelle/misc/setbits.cocci
--
2.16.4
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe @ 2018-09-07 19:41 ` Corentin Labbe 2018-09-10 5:16 ` Christophe LEROY 2018-09-07 19:41 ` [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h Corentin Labbe ` (5 subsequent siblings) 6 siblings, 1 reply; 15+ messages in thread From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw) To: linux-arm-kernel Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on the used data type. Signed-off-by: Corentin Labbe <clabbe@baylibre.com> --- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/io.h | 5 +- arch/powerpc/platforms/44x/canyonlands.c | 4 +- arch/powerpc/platforms/4xx/gpio.c | 28 ++++----- arch/powerpc/platforms/512x/pdm360ng.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +- arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 ++-- arch/powerpc/platforms/82xx/ep8248e.c | 2 +- arch/powerpc/platforms/82xx/km82xx.c | 6 +- arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 ++-- arch/powerpc/platforms/82xx/pq2.c | 2 +- arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +- arch/powerpc/platforms/82xx/pq2fads.c | 10 ++-- arch/powerpc/platforms/83xx/km83xx.c | 6 +- arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- arch/powerpc/platforms/85xx/p1022_ds.c | 4 +- arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +- arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +- arch/powerpc/platforms/85xx/twr_p102x.c | 2 +- arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +- arch/powerpc/platforms/8xx/adder875.c | 2 +- arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +- arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +- arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 ++++----- arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +- arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-- arch/powerpc/platforms/embedded6xx/wii.c | 10 ++-- arch/powerpc/sysdev/cpm1.c | 26 ++++----- arch/powerpc/sysdev/cpm2.c | 16 ++--- arch/powerpc/sysdev/cpm_common.c | 4 +- arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +-- arch/powerpc/sysdev/fsl_lbc.c | 2 +- arch/powerpc/sysdev/fsl_pci.c | 8 +-- arch/powerpc/sysdev/fsl_pmc.c | 2 +- arch/powerpc/sysdev/fsl_rcpm.c | 74 ++++++++++++------------ arch/powerpc/sysdev/fsl_rio.c | 4 +- arch/powerpc/sysdev/fsl_rmu.c | 8 +-- arch/powerpc/sysdev/mpic_timer.c | 12 ++-- 41 files changed, 178 insertions(+), 177 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index c7240a024b96..55d7aa0c27cf 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset) */ static inline void fsl_upm_end_pattern(struct fsl_upm *upm) { - clrbits32(upm->mxmr, MxMR_OP_RP); + clrbits32_be(upm->mxmr, MxMR_OP_RP); while (in_be32(upm->mxmr) & MxMR_OP_RP) cpu_relax(); diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index e0331e754568..29ecefd41ecb 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -873,8 +873,8 @@ static inline void * bus_to_virt(unsigned long address) #endif /* CONFIG_PPC32 */ /* access ports */ -#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) -#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) +#define setbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) +#define clrbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) @@ -904,6 +904,7 @@ static inline void * bus_to_virt(unsigned long address) #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define clrsetbits32_be(addr, clear, set) clrsetbits(be32, addr, clear, set) #endif /* __KERNEL__ */ diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c index 157f4ce46386..7145a730769d 100644 --- a/arch/powerpc/platforms/44x/canyonlands.c +++ b/arch/powerpc/platforms/44x/canyonlands.c @@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void) * USB2HStop and gpio19 will be USB2DStop. For more details refer to * table 34-7 of PPC460EX user manual. */ - setbits32((vaddr + GPIO0_OSRH), 0x42000000); - setbits32((vaddr + GPIO0_TSRH), 0x42000000); + setbits32_be((vaddr + GPIO0_OSRH), 0x42000000); + setbits32_be((vaddr + GPIO0_TSRH), 0x42000000); err_gpio: iounmap(vaddr); err_bcsr: diff --git a/arch/powerpc/platforms/4xx/gpio.c b/arch/powerpc/platforms/4xx/gpio.c index 2238e369cde4..e84f2d20674e 100644 --- a/arch/powerpc/platforms/4xx/gpio.c +++ b/arch/powerpc/platforms/4xx/gpio.c @@ -82,9 +82,9 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) struct ppc4xx_gpio __iomem *regs = mm_gc->regs; if (val) - setbits32(®s->or, GPIO_MASK(gpio)); + setbits32_be(®s->or, GPIO_MASK(gpio)); else - clrbits32(®s->or, GPIO_MASK(gpio)); + clrbits32_be(®s->or, GPIO_MASK(gpio)); } static void @@ -112,18 +112,18 @@ static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) spin_lock_irqsave(&chip->lock, flags); /* Disable open-drain function */ - clrbits32(®s->odr, GPIO_MASK(gpio)); + clrbits32_be(®s->odr, GPIO_MASK(gpio)); /* Float the pin */ - clrbits32(®s->tcr, GPIO_MASK(gpio)); + clrbits32_be(®s->tcr, GPIO_MASK(gpio)); /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ if (gpio < 16) { - clrbits32(®s->osrl, GPIO_MASK2(gpio)); - clrbits32(®s->tsrl, GPIO_MASK2(gpio)); + clrbits32_be(®s->osrl, GPIO_MASK2(gpio)); + clrbits32_be(®s->tsrl, GPIO_MASK2(gpio)); } else { - clrbits32(®s->osrh, GPIO_MASK2(gpio)); - clrbits32(®s->tsrh, GPIO_MASK2(gpio)); + clrbits32_be(®s->osrh, GPIO_MASK2(gpio)); + clrbits32_be(®s->tsrh, GPIO_MASK2(gpio)); } spin_unlock_irqrestore(&chip->lock, flags); @@ -145,18 +145,18 @@ ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) __ppc4xx_gpio_set(gc, gpio, val); /* Disable open-drain function */ - clrbits32(®s->odr, GPIO_MASK(gpio)); + clrbits32_be(®s->odr, GPIO_MASK(gpio)); /* Drive the pin */ - setbits32(®s->tcr, GPIO_MASK(gpio)); + setbits32_be(®s->tcr, GPIO_MASK(gpio)); /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ if (gpio < 16) { - clrbits32(®s->osrl, GPIO_MASK2(gpio)); - clrbits32(®s->tsrl, GPIO_MASK2(gpio)); + clrbits32_be(®s->osrl, GPIO_MASK2(gpio)); + clrbits32_be(®s->tsrl, GPIO_MASK2(gpio)); } else { - clrbits32(®s->osrh, GPIO_MASK2(gpio)); - clrbits32(®s->tsrh, GPIO_MASK2(gpio)); + clrbits32_be(®s->osrh, GPIO_MASK2(gpio)); + clrbits32_be(®s->tsrh, GPIO_MASK2(gpio)); } spin_unlock_irqrestore(&chip->lock, flags); diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c index dc81f05e0bce..283925e49096 100644 --- a/arch/powerpc/platforms/512x/pdm360ng.c +++ b/arch/powerpc/platforms/512x/pdm360ng.c @@ -38,7 +38,7 @@ static int pdm360ng_get_pendown_state(void) reg = in_be32(pdm360ng_gpio_base + 0xc); if (reg & 0x40) - setbits32(pdm360ng_gpio_base + 0xc, 0x40); + setbits32_be(pdm360ng_gpio_base + 0xc, 0x40); reg = in_be32(pdm360ng_gpio_base + 0x8); @@ -69,8 +69,8 @@ static int __init pdm360ng_penirq_init(void) return -ENODEV; } out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff); - setbits32(pdm360ng_gpio_base + 0x18, 0x2000); - setbits32(pdm360ng_gpio_base + 0x10, 0x40); + setbits32_be(pdm360ng_gpio_base + 0x18, 0x2000); + setbits32_be(pdm360ng_gpio_base + 0x10, 0x40); return 0; } diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c index 565e3a83dc9e..8a8b3d79798d 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c @@ -314,13 +314,13 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number) /* enable gpio pins for output */ setbits8(&wkup_gpio->wkup_gpioe, reset); - setbits32(&simple_gpio->simple_gpioe, sync | out); + setbits32_be(&simple_gpio->simple_gpioe, sync | out); setbits8(&wkup_gpio->wkup_ddr, reset); - setbits32(&simple_gpio->simple_ddr, sync | out); + setbits32_be(&simple_gpio->simple_ddr, sync | out); /* Assert cold reset */ - clrbits32(&simple_gpio->simple_dvo, sync | out); + clrbits32_be(&simple_gpio->simple_dvo, sync | out); clrbits8(&wkup_gpio->wkup_dvo, reset); /* wait for 1 us */ diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 17cf249b18ee..88eef86f802c 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -142,7 +142,7 @@ static void mpc52xx_gpt_irq_unmask(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(&gpt->lock, flags); - setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); + setbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); raw_spin_unlock_irqrestore(&gpt->lock, flags); } @@ -152,7 +152,7 @@ static void mpc52xx_gpt_irq_mask(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(&gpt->lock, flags); - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); + clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); raw_spin_unlock_irqrestore(&gpt->lock, flags); } @@ -308,7 +308,7 @@ static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); raw_spin_lock_irqsave(&gpt->lock, flags); - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); + clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); raw_spin_unlock_irqrestore(&gpt->lock, flags); return 0; @@ -482,7 +482,7 @@ int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt) return -EBUSY; } - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); + clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); raw_spin_unlock_irqrestore(&gpt->lock, flags); return 0; } @@ -639,7 +639,7 @@ static int mpc52xx_wdt_release(struct inode *inode, struct file *file) unsigned long flags; raw_spin_lock_irqsave(&gpt_wdt->lock, flags); - clrbits32(&gpt_wdt->regs->mode, + clrbits32_be(&gpt_wdt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN); gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags); diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c index 8fec050f2d5b..da4fee98085f 100644 --- a/arch/powerpc/platforms/82xx/ep8248e.c +++ b/arch/powerpc/platforms/82xx/ep8248e.c @@ -262,7 +262,7 @@ static void __init ep8248e_setup_arch(void) /* When this is set, snooping CPM DMA from RAM causes * machine checks. See erratum SIU18. */ - clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); + clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); ep8248e_bcsr_node = of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c index 28860e40b5db..b5b34f8b1a9b 100644 --- a/arch/powerpc/platforms/82xx/km82xx.c +++ b/arch/powerpc/platforms/82xx/km82xx.c @@ -157,9 +157,9 @@ static void __init init_ioports(void) cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); /* Force USB FULL SPEED bit to '1' */ - setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); + setbits32_be(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); /* clear USB_SLAVE */ - clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11)); + clrbits32_be(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11)); } static void __init km82xx_setup_arch(void) @@ -172,7 +172,7 @@ static void __init km82xx_setup_arch(void) /* When this is set, snooping CPM DMA from RAM causes * machine checks. See erratum SIU18. */ - clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); + clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); init_ioports(); diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c index d23c10a96bde..a9c8cd13a4b5 100644 --- a/arch/powerpc/platforms/82xx/mpc8272_ads.c +++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c @@ -164,13 +164,13 @@ static void __init mpc8272_ads_setup_arch(void) #define BCSR3_FETHIEN2 0x10000000 #define BCSR3_FETH2_RST 0x08000000 - clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); - setbits32(&bcsr[1], BCSR1_FETH_RST); + clrbits32_be(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); + setbits32_be(&bcsr[1], BCSR1_FETH_RST); - clrbits32(&bcsr[3], BCSR3_FETHIEN2); - setbits32(&bcsr[3], BCSR3_FETH2_RST); + clrbits32_be(&bcsr[3], BCSR3_FETHIEN2); + setbits32_be(&bcsr[3], BCSR3_FETH2_RST); - clrbits32(&bcsr[3], BCSR3_USB_nEN); + clrbits32_be(&bcsr[3], BCSR3_USB_nEN); iounmap(bcsr); diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c index c4f7029fc9ae..43a9a948f064 100644 --- a/arch/powerpc/platforms/82xx/pq2.c +++ b/arch/powerpc/platforms/82xx/pq2.c @@ -25,7 +25,7 @@ void __noreturn pq2_restart(char *cmd) { local_irq_disable(); - setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); + setbits32_be(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */ mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 8b065bdf7412..b691de4c580a 100644 --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c @@ -47,7 +47,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(&pci_pic_lock, flags); - setbits32(&priv->regs->mask, 1 << irq); + setbits32_be(&priv->regs->mask, 1 << irq); mb(); raw_spin_unlock_irqrestore(&pci_pic_lock, flags); @@ -63,7 +63,7 @@ static void pq2ads_pci_unmask_irq(struct irq_data *d) unsigned long flags; raw_spin_lock_irqsave(&pci_pic_lock, flags); - clrbits32(&priv->regs->mask, 1 << irq); + clrbits32_be(&priv->regs->mask, 1 << irq); raw_spin_unlock_irqrestore(&pci_pic_lock, flags); } } diff --git a/arch/powerpc/platforms/82xx/pq2fads.c b/arch/powerpc/platforms/82xx/pq2fads.c index 6c654dc74a4b..05e9c743712f 100644 --- a/arch/powerpc/platforms/82xx/pq2fads.c +++ b/arch/powerpc/platforms/82xx/pq2fads.c @@ -140,18 +140,18 @@ static void __init pq2fads_setup_arch(void) /* Enable the serial and ethernet ports */ - clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); - setbits32(&bcsr[1], BCSR1_FETH_RST); + clrbits32_be(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); + setbits32_be(&bcsr[1], BCSR1_FETH_RST); - clrbits32(&bcsr[3], BCSR3_FETHIEN2); - setbits32(&bcsr[3], BCSR3_FETH2_RST); + clrbits32_be(&bcsr[3], BCSR3_FETHIEN2); + setbits32_be(&bcsr[3], BCSR3_FETH2_RST); iounmap(bcsr); init_ioports(); /* Enable external IRQs */ - clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000); + clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000); pq2_init_pci(); diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c index d8642a4afc74..d13f11aac111 100644 --- a/arch/powerpc/platforms/83xx/km83xx.c +++ b/arch/powerpc/platforms/83xx/km83xx.c @@ -101,19 +101,19 @@ static void quirk_mpc8360e_qe_enet10(void) * UCC1: write 0b11 to bits 18:19 * at address IMMRBAR+0x14A8 */ - setbits32((base + 0xa8), 0x00003000); + setbits32_be((base + 0xa8), 0x00003000); /* * UCC2 option 1: write 0b11 to bits 4:5 * at address IMMRBAR+0x14A8 */ - setbits32((base + 0xa8), 0x0c000000); + setbits32_be((base + 0xa8), 0x0c000000); /* * UCC2 option 2: write 0b11 to bits 16:17 * at address IMMRBAR+0x14AC */ - setbits32((base + 0xac), 0x0000c000); + setbits32_be((base + 0xac), 0x0000c000); } iounmap(base); of_node_put(np_par); diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index fd44dd03e1f3..56e638fdbbc5 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -118,7 +118,7 @@ static void __init mpc836x_mds_setup_arch(void) * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ - setbits32(immap, 0x0c003000); + setbits32_be(immap, 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index d7e440e6dba3..06c18149dc5a 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -262,7 +262,7 @@ static void __init mpc85xx_mds_qe_init(void) * and QE12 for QE MII management signals in PMUXCR * register. */ - setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | + setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); diff --git a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c index f05325f0cc03..b1bb81a49a7f 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c @@ -60,9 +60,9 @@ static void mpc85xx_freeze_time_base(bool freeze) mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1; if (freeze) - setbits32(&guts->devdisr, mask); + setbits32_be(&guts->devdisr, mask); else - clrbits32(&guts->devdisr, mask); + clrbits32_be(&guts->devdisr, mask); in_be32(&guts->devdisr); } diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index 10069503e39f..13ae0b12dd5a 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -115,7 +115,7 @@ static void __init mpc85xx_rdb_setup_arch(void) * and QE12 for QE MII management singals in PMUXCR * register. */ - setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | + setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index 9fb57f78cdbe..adb7abdd291f 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -405,11 +405,11 @@ void p1022ds_set_pixel_clock(unsigned int pixclock) pxclk = clamp_t(u32, pxclk, 2, 255); /* Disable the pixel clock, and set it to non-inverted and no delay */ - clrbits32(&guts->clkdvdr, + clrbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); /* Enable the clock and set the pxclk */ - setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); + setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); iounmap(guts); } diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c index 276e00ab3dde..97698230f031 100644 --- a/arch/powerpc/platforms/85xx/p1022_rdk.c +++ b/arch/powerpc/platforms/85xx/p1022_rdk.c @@ -75,11 +75,11 @@ void p1022rdk_set_pixel_clock(unsigned int pixclock) pxclk = clamp_t(u32, pxclk, 2, 255); /* Disable the pixel clock, and set it to non-inverted and no delay */ - clrbits32(&guts->clkdvdr, + clrbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); /* Enable the clock and set the pxclk */ - setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); + setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); iounmap(guts); } diff --git a/arch/powerpc/platforms/85xx/t1042rdb_diu.c b/arch/powerpc/platforms/85xx/t1042rdb_diu.c index dac36ba82fea..c11f95711a8a 100644 --- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c +++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c @@ -114,11 +114,11 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock) pxclk = clamp_t(u32, pxclk, 2, 255); /* Disable the pixel clock, and set it to non-inverted and no delay */ - clrbits32(scfg + CCSR_SCFG_PIXCLKCR, + clrbits32_be(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK); /* Enable the clock and set the pxclk */ - setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16)); + setbits32_be(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16)); iounmap(scfg); } diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 360f6253e9ff..b678ee2665d0 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -95,7 +95,7 @@ static void __init twr_p1025_setup_arch(void) * and QE12 for QE MII management signals in PMUXCR * register. * Set QE mux bits in PMUXCR */ - setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | + setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c index a5d73fabe4d1..78472179b05a 100644 --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c @@ -261,11 +261,11 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) pxclk = clamp_t(u32, pxclk, 2, 31); /* Disable the pixel clock, and set it to non-inverted and no delay */ - clrbits32(&guts->clkdvdr, + clrbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); /* Enable the clock and set the pxclk */ - setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); + setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); iounmap(guts); } diff --git a/arch/powerpc/platforms/8xx/adder875.c b/arch/powerpc/platforms/8xx/adder875.c index bcef9f66191e..d21d0b8fd2a7 100644 --- a/arch/powerpc/platforms/8xx/adder875.c +++ b/arch/powerpc/platforms/8xx/adder875.c @@ -77,7 +77,7 @@ static void __init init_ioports(void) cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); /* Set FEC1 and FEC2 to MII mode */ - clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); + clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); } static void __init adder875_setup(void) diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index 027c42d8966c..2ed24abd0b40 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -103,7 +103,7 @@ void __init mpc8xx_calibrate_decr(void) /* Force all 8xx processors to use divide by 16 processor clock. */ clk_r2 = immr_map(im_clkrst); - setbits32(&clk_r2->car_sccr, 0x02000000); + setbits32_be(&clk_r2->car_sccr, 0x02000000); immr_unmap(clk_r2); /* Processor frequency is MHz. @@ -203,7 +203,7 @@ void __noreturn mpc8xx_restart(char *cmd) local_irq_disable(); - setbits32(&clk_r->car_plprcr, 0x00000080); + setbits32_be(&clk_r->car_plprcr, 0x00000080); /* Clear the ME bit in MSR to cause checkstop on machine check */ mtmsr(mfmsr() & ~0x1000); diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c index 8d02f5ff4481..a25e5ab15d65 100644 --- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c +++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c @@ -87,7 +87,7 @@ static void __init init_ioports(void) cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX); /* Set FEC1 and FEC2 to MII mode */ - clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); + clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); } static void __init mpc86xads_setup_arch(void) @@ -112,7 +112,7 @@ static void __init mpc86xads_setup_arch(void) return; } - clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN); + clrbits32_be(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN); iounmap(bcsr_io); } diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c index a0c83c1905c6..8aad0fb9090b 100644 --- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c +++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c @@ -123,7 +123,7 @@ static void __init init_ioports(void) cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX); /* Set FEC1 and FEC2 to MII mode */ - clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); + clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); } static void __init mpc885ads_setup_arch(void) @@ -148,33 +148,33 @@ static void __init mpc885ads_setup_arch(void) return; } - clrbits32(&bcsr[1], BCSR1_RS232EN_1); + clrbits32_be(&bcsr[1], BCSR1_RS232EN_1); #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 - setbits32(&bcsr[1], BCSR1_RS232EN_2); + setbits32_be(&bcsr[1], BCSR1_RS232EN_2); #else - clrbits32(&bcsr[1], BCSR1_RS232EN_2); + clrbits32_be(&bcsr[1], BCSR1_RS232EN_2); #endif - clrbits32(bcsr5, BCSR5_MII1_EN); - setbits32(bcsr5, BCSR5_MII1_RST); + clrbits32_be(bcsr5, BCSR5_MII1_EN); + setbits32_be(bcsr5, BCSR5_MII1_RST); udelay(1000); - clrbits32(bcsr5, BCSR5_MII1_RST); + clrbits32_be(bcsr5, BCSR5_MII1_RST); #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 - clrbits32(bcsr5, BCSR5_MII2_EN); - setbits32(bcsr5, BCSR5_MII2_RST); + clrbits32_be(bcsr5, BCSR5_MII2_EN); + setbits32_be(bcsr5, BCSR5_MII2_RST); udelay(1000); - clrbits32(bcsr5, BCSR5_MII2_RST); + clrbits32_be(bcsr5, BCSR5_MII2_RST); #else - setbits32(bcsr5, BCSR5_MII2_EN); + setbits32_be(bcsr5, BCSR5_MII2_EN); #endif #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 - clrbits32(&bcsr[4], BCSR4_ETH10_RST); + clrbits32_be(&bcsr[4], BCSR4_ETH10_RST); udelay(1000); - setbits32(&bcsr[4], BCSR4_ETH10_RST); + setbits32_be(&bcsr[4], BCSR4_ETH10_RST); - setbits32(&bcsr[1], BCSR1_ETHEN); + setbits32_be(&bcsr[1], BCSR1_ETHEN); np = of_find_node_by_path("/soc at ff000000/cpm at 9c0/serial at a80"); #else diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index db0be007fd06..6df4533aa851 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c @@ -53,7 +53,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d) void __iomem *io_base = irq_data_get_irq_chip_data(d); u32 mask = 1 << irq; - clrbits32(io_base + FLIPPER_IMR, mask); + clrbits32_be(io_base + FLIPPER_IMR, mask); /* this is@least needed for RSW */ out_be32(io_base + FLIPPER_ICR, mask); } @@ -72,7 +72,7 @@ static void flipper_pic_mask(struct irq_data *d) int irq = irqd_to_hwirq(d); void __iomem *io_base = irq_data_get_irq_chip_data(d); - clrbits32(io_base + FLIPPER_IMR, 1 << irq); + clrbits32_be(io_base + FLIPPER_IMR, 1 << irq); } static void flipper_pic_unmask(struct irq_data *d) @@ -80,7 +80,7 @@ static void flipper_pic_unmask(struct irq_data *d) int irq = irqd_to_hwirq(d); void __iomem *io_base = irq_data_get_irq_chip_data(d); - setbits32(io_base + FLIPPER_IMR, 1 << irq); + setbits32_be(io_base + FLIPPER_IMR, 1 << irq); } diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index 8112b39879d6..5487710bed1c 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c @@ -50,7 +50,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d) void __iomem *io_base = irq_data_get_irq_chip_data(d); u32 mask = 1 << irq; - clrbits32(io_base + HW_BROADWAY_IMR, mask); + clrbits32_be(io_base + HW_BROADWAY_IMR, mask); out_be32(io_base + HW_BROADWAY_ICR, mask); } @@ -67,7 +67,7 @@ static void hlwd_pic_mask(struct irq_data *d) int irq = irqd_to_hwirq(d); void __iomem *io_base = irq_data_get_irq_chip_data(d); - clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); + clrbits32_be(io_base + HW_BROADWAY_IMR, 1 << irq); } static void hlwd_pic_unmask(struct irq_data *d) @@ -75,10 +75,10 @@ static void hlwd_pic_unmask(struct irq_data *d) int irq = irqd_to_hwirq(d); void __iomem *io_base = irq_data_get_irq_chip_data(d); - setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); + setbits32_be(io_base + HW_BROADWAY_IMR, 1 << irq); /* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */ - clrbits32(io_base + HW_STARLET_IMR, 1 << irq); + clrbits32_be(io_base + HW_STARLET_IMR, 1 << irq); } diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c index 403523c061ba..dd511e19147a 100644 --- a/arch/powerpc/platforms/embedded6xx/wii.c +++ b/arch/powerpc/platforms/embedded6xx/wii.c @@ -134,7 +134,7 @@ static void __init wii_setup_arch(void) hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE); if (hw_gpio) { /* turn off the front blue led and IR light */ - clrbits32(hw_gpio + HW_GPIO_OUT(0), + clrbits32_be(hw_gpio + HW_GPIO_OUT(0), HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR); } } @@ -145,7 +145,7 @@ static void __noreturn wii_restart(char *cmd) if (hw_ctrl) { /* clear the system reset pin to cause a reset */ - clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS); + clrbits32_be(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS); } wii_spin(); } @@ -159,13 +159,13 @@ static void wii_power_off(void) * set the owner of the shutdown pin to ARM, because it is * accessed through the registers for the ARM, below */ - clrbits32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN); + clrbits32_be(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN); /* make sure that the poweroff GPIO is configured as output */ - setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN); + setbits32_be(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN); /* drive the poweroff GPIO high */ - setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN); + setbits32_be(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN); } wii_spin(); } diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c index 4f8dcf124828..9de5f13c51cb 100644 --- a/arch/powerpc/sysdev/cpm1.c +++ b/arch/powerpc/sysdev/cpm1.c @@ -60,14 +60,14 @@ static void cpm_mask_irq(struct irq_data *d) { unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); - clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); + clrbits32_be(&cpic_reg->cpic_cimr, (1 << cpm_vec)); } static void cpm_unmask_irq(struct irq_data *d) { unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); - setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); + setbits32_be(&cpic_reg->cpic_cimr, (1 << cpm_vec)); } static void cpm_end_irq(struct irq_data *d) @@ -188,7 +188,7 @@ unsigned int cpm_pic_init(void) if (setup_irq(eirq, &cpm_error_irqaction)) printk(KERN_ERR "Could not allocate CPM error IRQ!"); - setbits32(&cpic_reg->cpic_cicr, CICR_IEN); + setbits32_be(&cpic_reg->cpic_cicr, CICR_IEN); end: of_node_put(np); @@ -317,14 +317,14 @@ static void cpm1_set_pin32(int port, int pin, int flags) &mpc8xx_immr->im_cpm.cp_pedir; if (flags & CPM_PIN_OUTPUT) - setbits32(&iop->dir, pin); + setbits32_be(&iop->dir, pin); else - clrbits32(&iop->dir, pin); + clrbits32_be(&iop->dir, pin); if (!(flags & CPM_PIN_GPIO)) - setbits32(&iop->par, pin); + setbits32_be(&iop->par, pin); else - clrbits32(&iop->par, pin); + clrbits32_be(&iop->par, pin); if (port == CPM_PORTB) { if (flags & CPM_PIN_OPENDRAIN) @@ -335,14 +335,14 @@ static void cpm1_set_pin32(int port, int pin, int flags) if (port == CPM_PORTE) { if (flags & CPM_PIN_SECONDARY) - setbits32(&iop->sor, pin); + setbits32_be(&iop->sor, pin); else - clrbits32(&iop->sor, pin); + clrbits32_be(&iop->sor, pin); if (flags & CPM_PIN_OPENDRAIN) - setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); + setbits32_be(&mpc8xx_immr->im_cpm.cp_peodr, pin); else - clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); + clrbits32_be(&mpc8xx_immr->im_cpm.cp_peodr, pin); } } @@ -732,7 +732,7 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) spin_lock_irqsave(&cpm1_gc->lock, flags); - setbits32(&iop->dir, pin_mask); + setbits32_be(&iop->dir, pin_mask); __cpm1_gpio32_set(mm_gc, pin_mask, val); spin_unlock_irqrestore(&cpm1_gc->lock, flags); @@ -750,7 +750,7 @@ static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) spin_lock_irqsave(&cpm1_gc->lock, flags); - clrbits32(&iop->dir, pin_mask); + clrbits32_be(&iop->dir, pin_mask); spin_unlock_irqrestore(&cpm1_gc->lock, flags); diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c index 07718b9a2c99..445d6e45a6de 100644 --- a/arch/powerpc/sysdev/cpm2.c +++ b/arch/powerpc/sysdev/cpm2.c @@ -335,22 +335,22 @@ void cpm2_set_pin(int port, int pin, int flags) pin = 1 << (31 - pin); if (flags & CPM_PIN_OUTPUT) - setbits32(&iop[port].dir, pin); + setbits32_be(&iop[port].dir, pin); else - clrbits32(&iop[port].dir, pin); + clrbits32_be(&iop[port].dir, pin); if (!(flags & CPM_PIN_GPIO)) - setbits32(&iop[port].par, pin); + setbits32_be(&iop[port].par, pin); else - clrbits32(&iop[port].par, pin); + clrbits32_be(&iop[port].par, pin); if (flags & CPM_PIN_SECONDARY) - setbits32(&iop[port].sor, pin); + setbits32_be(&iop[port].sor, pin); else - clrbits32(&iop[port].sor, pin); + clrbits32_be(&iop[port].sor, pin); if (flags & CPM_PIN_OPENDRAIN) - setbits32(&iop[port].odr, pin); + setbits32_be(&iop[port].odr, pin); else - clrbits32(&iop[port].odr, pin); + clrbits32_be(&iop[port].odr, pin); } diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c index b74508175b67..d36a95708aaf 100644 --- a/arch/powerpc/sysdev/cpm_common.c +++ b/arch/powerpc/sysdev/cpm_common.c @@ -165,7 +165,7 @@ static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) spin_lock_irqsave(&cpm2_gc->lock, flags); - setbits32(&iop->dir, pin_mask); + setbits32_be(&iop->dir, pin_mask); __cpm2_gpio32_set(mm_gc, pin_mask, val); spin_unlock_irqrestore(&cpm2_gc->lock, flags); @@ -183,7 +183,7 @@ static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) spin_lock_irqsave(&cpm2_gc->lock, flags); - clrbits32(&iop->dir, pin_mask); + clrbits32_be(&iop->dir, pin_mask); spin_unlock_irqrestore(&cpm2_gc->lock, flags); diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c index c27058e5df26..2b7e2b4a2543 100644 --- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c +++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c @@ -124,23 +124,23 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev) switch (ways) { case LOCK_WAYS_EIGHTH: - setbits32(&l2ctlr->ctl, + setbits32_be(&l2ctlr->ctl, L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH); break; case LOCK_WAYS_TWO_EIGHTH: - setbits32(&l2ctlr->ctl, + setbits32_be(&l2ctlr->ctl, L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART); break; case LOCK_WAYS_HALF: - setbits32(&l2ctlr->ctl, + setbits32_be(&l2ctlr->ctl, L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF); break; case LOCK_WAYS_FULL: default: - setbits32(&l2ctlr->ctl, + setbits32_be(&l2ctlr->ctl, L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL); break; } diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c index 5340a483cf55..994233e41b91 100644 --- a/arch/powerpc/sysdev/fsl_lbc.c +++ b/arch/powerpc/sysdev/fsl_lbc.c @@ -192,7 +192,7 @@ static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl, struct fsl_lbc_regs __iomem *lbc = ctrl->regs; /* clear event registers */ - setbits32(&lbc->ltesr, LTESR_CLEAR); + setbits32_be(&lbc->ltesr, LTESR_CLEAR); out_be32(&lbc->lteatr, 0); out_be32(&lbc->ltear, 0); out_be32(&lbc->lteccr, LTECCR_CLEAR); diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 918be816b097..17aa5ee63d34 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1196,11 +1196,11 @@ static int fsl_pci_pme_probe(struct pci_controller *hose) pci = hose->private_data; /* Enable PTOD, ENL23D & EXL23D */ - clrbits32(&pci->pex_pme_mes_disr, + clrbits32_be(&pci->pex_pme_mes_disr, PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); out_be32(&pci->pex_pme_mes_ier, 0); - setbits32(&pci->pex_pme_mes_ier, + setbits32_be(&pci->pex_pme_mes_ier, PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); /* PME Enable */ @@ -1218,7 +1218,7 @@ static void send_pme_turnoff_message(struct pci_controller *hose) int i; /* Send PME_Turn_Off Message Request */ - setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); + setbits32_be(&pci->pex_pmcr, PEX_PMCR_PTOMR); /* Wait trun off done */ for (i = 0; i < 150; i++) { @@ -1254,7 +1254,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) int i; /* Send Exit L2 State Message */ - setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); + setbits32_be(&pci->pex_pmcr, PEX_PMCR_EXL2S); /* Wait exit done */ for (i = 0; i < 150; i++) { diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c index 232225e7f863..bbcf4cb89bb6 100644 --- a/arch/powerpc/sysdev/fsl_pmc.c +++ b/arch/powerpc/sysdev/fsl_pmc.c @@ -37,7 +37,7 @@ static int pmc_suspend_enter(suspend_state_t state) { int ret; - setbits32(&pmc_regs->pmcsr, PMCSR_SLP); + setbits32_be(&pmc_regs->pmcsr, PMCSR_SLP); /* At this point, the CPU is asleep. */ /* Upon resume, wait for SLP bit to be clear. */ diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c index 9259a94f70e1..bd2a7606bfce 100644 --- a/arch/powerpc/sysdev/fsl_rcpm.c +++ b/arch/powerpc/sysdev/fsl_rcpm.c @@ -33,10 +33,10 @@ static void rcpm_v1_irq_mask(int cpu) int hw_cpu = get_hard_smp_processor_id(cpu); unsigned int mask = 1 << hw_cpu; - setbits32(&rcpm_v1_regs->cpmimr, mask); - setbits32(&rcpm_v1_regs->cpmcimr, mask); - setbits32(&rcpm_v1_regs->cpmmcmr, mask); - setbits32(&rcpm_v1_regs->cpmnmimr, mask); + setbits32_be(&rcpm_v1_regs->cpmimr, mask); + setbits32_be(&rcpm_v1_regs->cpmcimr, mask); + setbits32_be(&rcpm_v1_regs->cpmmcmr, mask); + setbits32_be(&rcpm_v1_regs->cpmnmimr, mask); } static void rcpm_v2_irq_mask(int cpu) @@ -44,10 +44,10 @@ static void rcpm_v2_irq_mask(int cpu) int hw_cpu = get_hard_smp_processor_id(cpu); unsigned int mask = 1 << hw_cpu; - setbits32(&rcpm_v2_regs->tpmimr0, mask); - setbits32(&rcpm_v2_regs->tpmcimr0, mask); - setbits32(&rcpm_v2_regs->tpmmcmr0, mask); - setbits32(&rcpm_v2_regs->tpmnmimr0, mask); + setbits32_be(&rcpm_v2_regs->tpmimr0, mask); + setbits32_be(&rcpm_v2_regs->tpmcimr0, mask); + setbits32_be(&rcpm_v2_regs->tpmmcmr0, mask); + setbits32_be(&rcpm_v2_regs->tpmnmimr0, mask); } static void rcpm_v1_irq_unmask(int cpu) @@ -55,10 +55,10 @@ static void rcpm_v1_irq_unmask(int cpu) int hw_cpu = get_hard_smp_processor_id(cpu); unsigned int mask = 1 << hw_cpu; - clrbits32(&rcpm_v1_regs->cpmimr, mask); - clrbits32(&rcpm_v1_regs->cpmcimr, mask); - clrbits32(&rcpm_v1_regs->cpmmcmr, mask); - clrbits32(&rcpm_v1_regs->cpmnmimr, mask); + clrbits32_be(&rcpm_v1_regs->cpmimr, mask); + clrbits32_be(&rcpm_v1_regs->cpmcimr, mask); + clrbits32_be(&rcpm_v1_regs->cpmmcmr, mask); + clrbits32_be(&rcpm_v1_regs->cpmnmimr, mask); } static void rcpm_v2_irq_unmask(int cpu) @@ -66,26 +66,26 @@ static void rcpm_v2_irq_unmask(int cpu) int hw_cpu = get_hard_smp_processor_id(cpu); unsigned int mask = 1 << hw_cpu; - clrbits32(&rcpm_v2_regs->tpmimr0, mask); - clrbits32(&rcpm_v2_regs->tpmcimr0, mask); - clrbits32(&rcpm_v2_regs->tpmmcmr0, mask); - clrbits32(&rcpm_v2_regs->tpmnmimr0, mask); + clrbits32_be(&rcpm_v2_regs->tpmimr0, mask); + clrbits32_be(&rcpm_v2_regs->tpmcimr0, mask); + clrbits32_be(&rcpm_v2_regs->tpmmcmr0, mask); + clrbits32_be(&rcpm_v2_regs->tpmnmimr0, mask); } static void rcpm_v1_set_ip_power(bool enable, u32 mask) { if (enable) - setbits32(&rcpm_v1_regs->ippdexpcr, mask); + setbits32_be(&rcpm_v1_regs->ippdexpcr, mask); else - clrbits32(&rcpm_v1_regs->ippdexpcr, mask); + clrbits32_be(&rcpm_v1_regs->ippdexpcr, mask); } static void rcpm_v2_set_ip_power(bool enable, u32 mask) { if (enable) - setbits32(&rcpm_v2_regs->ippdexpcr[0], mask); + setbits32_be(&rcpm_v2_regs->ippdexpcr[0], mask); else - clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask); + clrbits32_be(&rcpm_v2_regs->ippdexpcr[0], mask); } static void rcpm_v1_cpu_enter_state(int cpu, int state) @@ -95,10 +95,10 @@ static void rcpm_v1_cpu_enter_state(int cpu, int state) switch (state) { case E500_PM_PH10: - setbits32(&rcpm_v1_regs->cdozcr, mask); + setbits32_be(&rcpm_v1_regs->cdozcr, mask); break; case E500_PM_PH15: - setbits32(&rcpm_v1_regs->cnapcr, mask); + setbits32_be(&rcpm_v1_regs->cnapcr, mask); break; default: pr_warn("Unknown cpu PM state (%d)\n", state); @@ -114,16 +114,16 @@ static void rcpm_v2_cpu_enter_state(int cpu, int state) switch (state) { case E500_PM_PH10: /* one bit corresponds to one thread for PH10 of 6500 */ - setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu); + setbits32_be(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu); break; case E500_PM_PH15: - setbits32(&rcpm_v2_regs->pcph15setr, mask); + setbits32_be(&rcpm_v2_regs->pcph15setr, mask); break; case E500_PM_PH20: - setbits32(&rcpm_v2_regs->pcph20setr, mask); + setbits32_be(&rcpm_v2_regs->pcph20setr, mask); break; case E500_PM_PH30: - setbits32(&rcpm_v2_regs->pcph30setr, mask); + setbits32_be(&rcpm_v2_regs->pcph30setr, mask); break; default: pr_warn("Unknown cpu PM state (%d)\n", state); @@ -172,10 +172,10 @@ static void rcpm_v1_cpu_exit_state(int cpu, int state) switch (state) { case E500_PM_PH10: - clrbits32(&rcpm_v1_regs->cdozcr, mask); + clrbits32_be(&rcpm_v1_regs->cdozcr, mask); break; case E500_PM_PH15: - clrbits32(&rcpm_v1_regs->cnapcr, mask); + clrbits32_be(&rcpm_v1_regs->cnapcr, mask); break; default: pr_warn("Unknown cpu PM state (%d)\n", state); @@ -196,16 +196,16 @@ static void rcpm_v2_cpu_exit_state(int cpu, int state) switch (state) { case E500_PM_PH10: - setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu); + setbits32_be(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu); break; case E500_PM_PH15: - setbits32(&rcpm_v2_regs->pcph15clrr, mask); + setbits32_be(&rcpm_v2_regs->pcph15clrr, mask); break; case E500_PM_PH20: - setbits32(&rcpm_v2_regs->pcph20clrr, mask); + setbits32_be(&rcpm_v2_regs->pcph20clrr, mask); break; case E500_PM_PH30: - setbits32(&rcpm_v2_regs->pcph30clrr, mask); + setbits32_be(&rcpm_v2_regs->pcph30clrr, mask); break; default: pr_warn("Unknown cpu PM state (%d)\n", state); @@ -226,7 +226,7 @@ static int rcpm_v1_plat_enter_state(int state) switch (state) { case PLAT_PM_SLEEP: - setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP); + setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_SLP); /* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */ result = spin_event_timeout( @@ -253,9 +253,9 @@ static int rcpm_v2_plat_enter_state(int state) switch (state) { case PLAT_PM_LPM20: /* clear previous LPM20 status */ - setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST); + setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST); /* enter LPM20 status */ - setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ); + setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ); /* At this point, the device is in LPM20 status. */ @@ -291,9 +291,9 @@ static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze) if (freeze) { mask = in_be32(tben_reg); - clrbits32(tben_reg, mask); + clrbits32_be(tben_reg, mask); } else { - setbits32(tben_reg, mask); + setbits32_be(tben_reg, mask); } /* read back to push the previous write */ diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index 5011ffea4e4b..278e63cc8afe 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -668,10 +668,10 @@ int fsl_rio_setup(struct platform_device *dev) out_be32(priv->regs_win + RIO_CCSR + i*0x20, 0); /* Set 1x lane */ - setbits32(priv->regs_win + setbits32_be(priv->regs_win + RIO_CCSR + i*0x20, 0x02000000); /* Enable ports */ - setbits32(priv->regs_win + setbits32_be(priv->regs_win + RIO_CCSR + i*0x20, 0x00600000); msleep(100); if (in_be32((priv->regs_win diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c index 88b35a3dcdc5..134ba53f0fcb 100644 --- a/arch/powerpc/sysdev/fsl_rmu.c +++ b/arch/powerpc/sysdev/fsl_rmu.c @@ -355,7 +355,7 @@ fsl_rio_dbell_handler(int irq, void *dev_instance) dmsg->sid, dmsg->tid, dmsg->info); } - setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); + setbits32_be(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); } @@ -909,10 +909,10 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) out_be32(&rmu->msg_regs->imr, 0x001b0060); /* Set number of queue entries */ - setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); + setbits32_be(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); /* Now enable the unit */ - setbits32(&rmu->msg_regs->imr, 0x1); + setbits32_be(&rmu->msg_regs->imr, 0x1); out: return rc; @@ -1015,7 +1015,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox) rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; out1: - setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); + setbits32_be(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); out2: return buf; diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c index 87e7c42777a8..70b02ba90220 100644 --- a/arch/powerpc/sysdev/mpic_timer.c +++ b/arch/powerpc/sysdev/mpic_timer.c @@ -154,7 +154,7 @@ static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks, tcr = casc_priv->tcr_value | (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET); - setbits32(priv->group_tcr, tcr); + setbits32_be(priv->group_tcr, tcr); tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks); @@ -253,7 +253,7 @@ void mpic_start_timer(struct mpic_timer *handle) struct timer_group_priv *priv = container_of(handle, struct timer_group_priv, timer[handle->num]); - clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); + clrbits32_be(&priv->regs[handle->num].gtbcr, TIMER_STOP); } EXPORT_SYMBOL(mpic_start_timer); @@ -269,7 +269,7 @@ void mpic_stop_timer(struct mpic_timer *handle) struct timer_group_priv, timer[handle->num]); struct cascade_priv *casc_priv; - setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); + setbits32_be(&priv->regs[handle->num].gtbcr, TIMER_STOP); casc_priv = priv->timer[handle->num].cascade_handle; if (casc_priv) { @@ -340,7 +340,7 @@ void mpic_free_timer(struct mpic_timer *handle) u32 tcr; tcr = casc_priv->tcr_value | (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET); - clrbits32(priv->group_tcr, tcr); + clrbits32_be(priv->group_tcr, tcr); priv->idle |= casc_priv->cascade_map; priv->timer[handle->num].cascade_handle = NULL; } else { @@ -508,7 +508,7 @@ static void timer_group_init(struct device_node *np) /* Init FSL timer hardware */ if (priv->flags & FSL_GLOBAL_TIMER) - setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); + setbits32_be(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); list_add_tail(&priv->node, &timer_group_list); @@ -531,7 +531,7 @@ static void mpic_timer_resume(void) list_for_each_entry(priv, &timer_group_list, node) { /* Init FSL timer hardware */ if (priv->flags & FSL_GLOBAL_TIMER) - setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); + setbits32_be(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); } } -- 2.16.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be 2018-09-07 19:41 ` [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be Corentin Labbe @ 2018-09-10 5:16 ` Christophe LEROY 2018-09-10 18:50 ` LABBE Corentin 0 siblings, 1 reply; 15+ messages in thread From: Christophe LEROY @ 2018-09-10 5:16 UTC (permalink / raw) To: linux-arm-kernel Le 07/09/2018 ? 21:41, Corentin Labbe a ?crit?: > Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on > the used data type. Wouldn't it be better to call them setbits_be32() / clrbits_be32() to have something looking similar to in_be32() / ou_be32() ? Christophe > > Signed-off-by: Corentin Labbe <clabbe@baylibre.com> > --- > arch/powerpc/include/asm/fsl_lbc.h | 2 +- > arch/powerpc/include/asm/io.h | 5 +- > arch/powerpc/platforms/44x/canyonlands.c | 4 +- > arch/powerpc/platforms/4xx/gpio.c | 28 ++++----- > arch/powerpc/platforms/512x/pdm360ng.c | 6 +- > arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +- > arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 ++-- > arch/powerpc/platforms/82xx/ep8248e.c | 2 +- > arch/powerpc/platforms/82xx/km82xx.c | 6 +- > arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 ++-- > arch/powerpc/platforms/82xx/pq2.c | 2 +- > arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +- > arch/powerpc/platforms/82xx/pq2fads.c | 10 ++-- > arch/powerpc/platforms/83xx/km83xx.c | 6 +- > arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- > arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +- > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- > arch/powerpc/platforms/85xx/p1022_ds.c | 4 +- > arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +- > arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +- > arch/powerpc/platforms/85xx/twr_p102x.c | 2 +- > arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +- > arch/powerpc/platforms/8xx/adder875.c | 2 +- > arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +- > arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +- > arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 ++++----- > arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +- > arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-- > arch/powerpc/platforms/embedded6xx/wii.c | 10 ++-- > arch/powerpc/sysdev/cpm1.c | 26 ++++----- > arch/powerpc/sysdev/cpm2.c | 16 ++--- > arch/powerpc/sysdev/cpm_common.c | 4 +- > arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +-- > arch/powerpc/sysdev/fsl_lbc.c | 2 +- > arch/powerpc/sysdev/fsl_pci.c | 8 +-- > arch/powerpc/sysdev/fsl_pmc.c | 2 +- > arch/powerpc/sysdev/fsl_rcpm.c | 74 ++++++++++++------------ > arch/powerpc/sysdev/fsl_rio.c | 4 +- > arch/powerpc/sysdev/fsl_rmu.c | 8 +-- > arch/powerpc/sysdev/mpic_timer.c | 12 ++-- > 41 files changed, 178 insertions(+), 177 deletions(-) > > diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h > index c7240a024b96..55d7aa0c27cf 100644 > --- a/arch/powerpc/include/asm/fsl_lbc.h > +++ b/arch/powerpc/include/asm/fsl_lbc.h > @@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset) > */ > static inline void fsl_upm_end_pattern(struct fsl_upm *upm) > { > - clrbits32(upm->mxmr, MxMR_OP_RP); > + clrbits32_be(upm->mxmr, MxMR_OP_RP); > > while (in_be32(upm->mxmr) & MxMR_OP_RP) > cpu_relax(); > diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h > index e0331e754568..29ecefd41ecb 100644 > --- a/arch/powerpc/include/asm/io.h > +++ b/arch/powerpc/include/asm/io.h > @@ -873,8 +873,8 @@ static inline void * bus_to_virt(unsigned long address) > #endif /* CONFIG_PPC32 */ > > /* access ports */ > -#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) > -#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) > +#define setbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) > +#define clrbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) > > #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) > #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) > @@ -904,6 +904,7 @@ static inline void * bus_to_virt(unsigned long address) > #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) > > #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) > +#define clrsetbits32_be(addr, clear, set) clrsetbits(be32, addr, clear, set) > > #endif /* __KERNEL__ */ > > diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c > index 157f4ce46386..7145a730769d 100644 > --- a/arch/powerpc/platforms/44x/canyonlands.c > +++ b/arch/powerpc/platforms/44x/canyonlands.c > @@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void) > * USB2HStop and gpio19 will be USB2DStop. For more details refer to > * table 34-7 of PPC460EX user manual. > */ > - setbits32((vaddr + GPIO0_OSRH), 0x42000000); > - setbits32((vaddr + GPIO0_TSRH), 0x42000000); > + setbits32_be((vaddr + GPIO0_OSRH), 0x42000000); > + setbits32_be((vaddr + GPIO0_TSRH), 0x42000000); > err_gpio: > iounmap(vaddr); > err_bcsr: > diff --git a/arch/powerpc/platforms/4xx/gpio.c b/arch/powerpc/platforms/4xx/gpio.c > index 2238e369cde4..e84f2d20674e 100644 > --- a/arch/powerpc/platforms/4xx/gpio.c > +++ b/arch/powerpc/platforms/4xx/gpio.c > @@ -82,9 +82,9 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) > struct ppc4xx_gpio __iomem *regs = mm_gc->regs; > > if (val) > - setbits32(®s->or, GPIO_MASK(gpio)); > + setbits32_be(®s->or, GPIO_MASK(gpio)); > else > - clrbits32(®s->or, GPIO_MASK(gpio)); > + clrbits32_be(®s->or, GPIO_MASK(gpio)); > } > > static void > @@ -112,18 +112,18 @@ static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) > spin_lock_irqsave(&chip->lock, flags); > > /* Disable open-drain function */ > - clrbits32(®s->odr, GPIO_MASK(gpio)); > + clrbits32_be(®s->odr, GPIO_MASK(gpio)); > > /* Float the pin */ > - clrbits32(®s->tcr, GPIO_MASK(gpio)); > + clrbits32_be(®s->tcr, GPIO_MASK(gpio)); > > /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ > if (gpio < 16) { > - clrbits32(®s->osrl, GPIO_MASK2(gpio)); > - clrbits32(®s->tsrl, GPIO_MASK2(gpio)); > + clrbits32_be(®s->osrl, GPIO_MASK2(gpio)); > + clrbits32_be(®s->tsrl, GPIO_MASK2(gpio)); > } else { > - clrbits32(®s->osrh, GPIO_MASK2(gpio)); > - clrbits32(®s->tsrh, GPIO_MASK2(gpio)); > + clrbits32_be(®s->osrh, GPIO_MASK2(gpio)); > + clrbits32_be(®s->tsrh, GPIO_MASK2(gpio)); > } > > spin_unlock_irqrestore(&chip->lock, flags); > @@ -145,18 +145,18 @@ ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) > __ppc4xx_gpio_set(gc, gpio, val); > > /* Disable open-drain function */ > - clrbits32(®s->odr, GPIO_MASK(gpio)); > + clrbits32_be(®s->odr, GPIO_MASK(gpio)); > > /* Drive the pin */ > - setbits32(®s->tcr, GPIO_MASK(gpio)); > + setbits32_be(®s->tcr, GPIO_MASK(gpio)); > > /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ > if (gpio < 16) { > - clrbits32(®s->osrl, GPIO_MASK2(gpio)); > - clrbits32(®s->tsrl, GPIO_MASK2(gpio)); > + clrbits32_be(®s->osrl, GPIO_MASK2(gpio)); > + clrbits32_be(®s->tsrl, GPIO_MASK2(gpio)); > } else { > - clrbits32(®s->osrh, GPIO_MASK2(gpio)); > - clrbits32(®s->tsrh, GPIO_MASK2(gpio)); > + clrbits32_be(®s->osrh, GPIO_MASK2(gpio)); > + clrbits32_be(®s->tsrh, GPIO_MASK2(gpio)); > } > > spin_unlock_irqrestore(&chip->lock, flags); > diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c > index dc81f05e0bce..283925e49096 100644 > --- a/arch/powerpc/platforms/512x/pdm360ng.c > +++ b/arch/powerpc/platforms/512x/pdm360ng.c > @@ -38,7 +38,7 @@ static int pdm360ng_get_pendown_state(void) > > reg = in_be32(pdm360ng_gpio_base + 0xc); > if (reg & 0x40) > - setbits32(pdm360ng_gpio_base + 0xc, 0x40); > + setbits32_be(pdm360ng_gpio_base + 0xc, 0x40); > > reg = in_be32(pdm360ng_gpio_base + 0x8); > > @@ -69,8 +69,8 @@ static int __init pdm360ng_penirq_init(void) > return -ENODEV; > } > out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff); > - setbits32(pdm360ng_gpio_base + 0x18, 0x2000); > - setbits32(pdm360ng_gpio_base + 0x10, 0x40); > + setbits32_be(pdm360ng_gpio_base + 0x18, 0x2000); > + setbits32_be(pdm360ng_gpio_base + 0x10, 0x40); > > return 0; > } > diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c > index 565e3a83dc9e..8a8b3d79798d 100644 > --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c > +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c > @@ -314,13 +314,13 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number) > > /* enable gpio pins for output */ > setbits8(&wkup_gpio->wkup_gpioe, reset); > - setbits32(&simple_gpio->simple_gpioe, sync | out); > + setbits32_be(&simple_gpio->simple_gpioe, sync | out); > > setbits8(&wkup_gpio->wkup_ddr, reset); > - setbits32(&simple_gpio->simple_ddr, sync | out); > + setbits32_be(&simple_gpio->simple_ddr, sync | out); > > /* Assert cold reset */ > - clrbits32(&simple_gpio->simple_dvo, sync | out); > + clrbits32_be(&simple_gpio->simple_dvo, sync | out); > clrbits8(&wkup_gpio->wkup_dvo, reset); > > /* wait for 1 us */ > diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c > index 17cf249b18ee..88eef86f802c 100644 > --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c > +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c > @@ -142,7 +142,7 @@ static void mpc52xx_gpt_irq_unmask(struct irq_data *d) > unsigned long flags; > > raw_spin_lock_irqsave(&gpt->lock, flags); > - setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); > + setbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); > raw_spin_unlock_irqrestore(&gpt->lock, flags); > } > > @@ -152,7 +152,7 @@ static void mpc52xx_gpt_irq_mask(struct irq_data *d) > unsigned long flags; > > raw_spin_lock_irqsave(&gpt->lock, flags); > - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); > + clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); > raw_spin_unlock_irqrestore(&gpt->lock, flags); > } > > @@ -308,7 +308,7 @@ static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) > dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); > > raw_spin_lock_irqsave(&gpt->lock, flags); > - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); > + clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); > raw_spin_unlock_irqrestore(&gpt->lock, flags); > > return 0; > @@ -482,7 +482,7 @@ int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt) > return -EBUSY; > } > > - clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); > + clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); > raw_spin_unlock_irqrestore(&gpt->lock, flags); > return 0; > } > @@ -639,7 +639,7 @@ static int mpc52xx_wdt_release(struct inode *inode, struct file *file) > unsigned long flags; > > raw_spin_lock_irqsave(&gpt_wdt->lock, flags); > - clrbits32(&gpt_wdt->regs->mode, > + clrbits32_be(&gpt_wdt->regs->mode, > MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN); > gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; > raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags); > diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c > index 8fec050f2d5b..da4fee98085f 100644 > --- a/arch/powerpc/platforms/82xx/ep8248e.c > +++ b/arch/powerpc/platforms/82xx/ep8248e.c > @@ -262,7 +262,7 @@ static void __init ep8248e_setup_arch(void) > /* When this is set, snooping CPM DMA from RAM causes > * machine checks. See erratum SIU18. > */ > - clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); > + clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); > > ep8248e_bcsr_node = > of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); > diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c > index 28860e40b5db..b5b34f8b1a9b 100644 > --- a/arch/powerpc/platforms/82xx/km82xx.c > +++ b/arch/powerpc/platforms/82xx/km82xx.c > @@ -157,9 +157,9 @@ static void __init init_ioports(void) > cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); > > /* Force USB FULL SPEED bit to '1' */ > - setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); > + setbits32_be(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); > /* clear USB_SLAVE */ > - clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11)); > + clrbits32_be(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11)); > } > > static void __init km82xx_setup_arch(void) > @@ -172,7 +172,7 @@ static void __init km82xx_setup_arch(void) > /* When this is set, snooping CPM DMA from RAM causes > * machine checks. See erratum SIU18. > */ > - clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); > + clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); > > init_ioports(); > > diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c > index d23c10a96bde..a9c8cd13a4b5 100644 > --- a/arch/powerpc/platforms/82xx/mpc8272_ads.c > +++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c > @@ -164,13 +164,13 @@ static void __init mpc8272_ads_setup_arch(void) > #define BCSR3_FETHIEN2 0x10000000 > #define BCSR3_FETH2_RST 0x08000000 > > - clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); > - setbits32(&bcsr[1], BCSR1_FETH_RST); > + clrbits32_be(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); > + setbits32_be(&bcsr[1], BCSR1_FETH_RST); > > - clrbits32(&bcsr[3], BCSR3_FETHIEN2); > - setbits32(&bcsr[3], BCSR3_FETH2_RST); > + clrbits32_be(&bcsr[3], BCSR3_FETHIEN2); > + setbits32_be(&bcsr[3], BCSR3_FETH2_RST); > > - clrbits32(&bcsr[3], BCSR3_USB_nEN); > + clrbits32_be(&bcsr[3], BCSR3_USB_nEN); > > iounmap(bcsr); > > diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c > index c4f7029fc9ae..43a9a948f064 100644 > --- a/arch/powerpc/platforms/82xx/pq2.c > +++ b/arch/powerpc/platforms/82xx/pq2.c > @@ -25,7 +25,7 @@ > void __noreturn pq2_restart(char *cmd) > { > local_irq_disable(); > - setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); > + setbits32_be(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); > > /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */ > mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); > diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c > index 8b065bdf7412..b691de4c580a 100644 > --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c > +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c > @@ -47,7 +47,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d) > unsigned long flags; > raw_spin_lock_irqsave(&pci_pic_lock, flags); > > - setbits32(&priv->regs->mask, 1 << irq); > + setbits32_be(&priv->regs->mask, 1 << irq); > mb(); > > raw_spin_unlock_irqrestore(&pci_pic_lock, flags); > @@ -63,7 +63,7 @@ static void pq2ads_pci_unmask_irq(struct irq_data *d) > unsigned long flags; > > raw_spin_lock_irqsave(&pci_pic_lock, flags); > - clrbits32(&priv->regs->mask, 1 << irq); > + clrbits32_be(&priv->regs->mask, 1 << irq); > raw_spin_unlock_irqrestore(&pci_pic_lock, flags); > } > } > diff --git a/arch/powerpc/platforms/82xx/pq2fads.c b/arch/powerpc/platforms/82xx/pq2fads.c > index 6c654dc74a4b..05e9c743712f 100644 > --- a/arch/powerpc/platforms/82xx/pq2fads.c > +++ b/arch/powerpc/platforms/82xx/pq2fads.c > @@ -140,18 +140,18 @@ static void __init pq2fads_setup_arch(void) > > /* Enable the serial and ethernet ports */ > > - clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); > - setbits32(&bcsr[1], BCSR1_FETH_RST); > + clrbits32_be(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); > + setbits32_be(&bcsr[1], BCSR1_FETH_RST); > > - clrbits32(&bcsr[3], BCSR3_FETHIEN2); > - setbits32(&bcsr[3], BCSR3_FETH2_RST); > + clrbits32_be(&bcsr[3], BCSR3_FETHIEN2); > + setbits32_be(&bcsr[3], BCSR3_FETH2_RST); > > iounmap(bcsr); > > init_ioports(); > > /* Enable external IRQs */ > - clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000); > + clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000); > > pq2_init_pci(); > > diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c > index d8642a4afc74..d13f11aac111 100644 > --- a/arch/powerpc/platforms/83xx/km83xx.c > +++ b/arch/powerpc/platforms/83xx/km83xx.c > @@ -101,19 +101,19 @@ static void quirk_mpc8360e_qe_enet10(void) > * UCC1: write 0b11 to bits 18:19 > * at address IMMRBAR+0x14A8 > */ > - setbits32((base + 0xa8), 0x00003000); > + setbits32_be((base + 0xa8), 0x00003000); > > /* > * UCC2 option 1: write 0b11 to bits 4:5 > * at address IMMRBAR+0x14A8 > */ > - setbits32((base + 0xa8), 0x0c000000); > + setbits32_be((base + 0xa8), 0x0c000000); > > /* > * UCC2 option 2: write 0b11 to bits 16:17 > * at address IMMRBAR+0x14AC > */ > - setbits32((base + 0xac), 0x0000c000); > + setbits32_be((base + 0xac), 0x0000c000); > } > iounmap(base); > of_node_put(np_par); > diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c > index fd44dd03e1f3..56e638fdbbc5 100644 > --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c > +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c > @@ -118,7 +118,7 @@ static void __init mpc836x_mds_setup_arch(void) > * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) > * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) > */ > - setbits32(immap, 0x0c003000); > + setbits32_be(immap, 0x0c003000); > > /* > * IMMR + 0x14AC[20:27] = 10101010 > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c > index d7e440e6dba3..06c18149dc5a 100644 > --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c > +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c > @@ -262,7 +262,7 @@ static void __init mpc85xx_mds_qe_init(void) > * and QE12 for QE MII management signals in PMUXCR > * register. > */ > - setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > + setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > MPC85xx_PMUXCR_QE(3) | > MPC85xx_PMUXCR_QE(9) | > MPC85xx_PMUXCR_QE(12)); > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c > index f05325f0cc03..b1bb81a49a7f 100644 > --- a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c > +++ b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c > @@ -60,9 +60,9 @@ static void mpc85xx_freeze_time_base(bool freeze) > > mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1; > if (freeze) > - setbits32(&guts->devdisr, mask); > + setbits32_be(&guts->devdisr, mask); > else > - clrbits32(&guts->devdisr, mask); > + clrbits32_be(&guts->devdisr, mask); > > in_be32(&guts->devdisr); > } > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > index 10069503e39f..13ae0b12dd5a 100644 > --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c > @@ -115,7 +115,7 @@ static void __init mpc85xx_rdb_setup_arch(void) > * and QE12 for QE MII management singals in PMUXCR > * register. > */ > - setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > + setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > MPC85xx_PMUXCR_QE(3) | > MPC85xx_PMUXCR_QE(9) | > MPC85xx_PMUXCR_QE(12)); > diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c > index 9fb57f78cdbe..adb7abdd291f 100644 > --- a/arch/powerpc/platforms/85xx/p1022_ds.c > +++ b/arch/powerpc/platforms/85xx/p1022_ds.c > @@ -405,11 +405,11 @@ void p1022ds_set_pixel_clock(unsigned int pixclock) > pxclk = clamp_t(u32, pxclk, 2, 255); > > /* Disable the pixel clock, and set it to non-inverted and no delay */ > - clrbits32(&guts->clkdvdr, > + clrbits32_be(&guts->clkdvdr, > CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); > > /* Enable the clock and set the pxclk */ > - setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); > + setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); > > iounmap(guts); > } > diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c > index 276e00ab3dde..97698230f031 100644 > --- a/arch/powerpc/platforms/85xx/p1022_rdk.c > +++ b/arch/powerpc/platforms/85xx/p1022_rdk.c > @@ -75,11 +75,11 @@ void p1022rdk_set_pixel_clock(unsigned int pixclock) > pxclk = clamp_t(u32, pxclk, 2, 255); > > /* Disable the pixel clock, and set it to non-inverted and no delay */ > - clrbits32(&guts->clkdvdr, > + clrbits32_be(&guts->clkdvdr, > CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); > > /* Enable the clock and set the pxclk */ > - setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); > + setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); > > iounmap(guts); > } > diff --git a/arch/powerpc/platforms/85xx/t1042rdb_diu.c b/arch/powerpc/platforms/85xx/t1042rdb_diu.c > index dac36ba82fea..c11f95711a8a 100644 > --- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c > +++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c > @@ -114,11 +114,11 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock) > pxclk = clamp_t(u32, pxclk, 2, 255); > > /* Disable the pixel clock, and set it to non-inverted and no delay */ > - clrbits32(scfg + CCSR_SCFG_PIXCLKCR, > + clrbits32_be(scfg + CCSR_SCFG_PIXCLKCR, > PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK); > > /* Enable the clock and set the pxclk */ > - setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16)); > + setbits32_be(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16)); > > iounmap(scfg); > } > diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c > index 360f6253e9ff..b678ee2665d0 100644 > --- a/arch/powerpc/platforms/85xx/twr_p102x.c > +++ b/arch/powerpc/platforms/85xx/twr_p102x.c > @@ -95,7 +95,7 @@ static void __init twr_p1025_setup_arch(void) > * and QE12 for QE MII management signals in PMUXCR > * register. > * Set QE mux bits in PMUXCR */ > - setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > + setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > MPC85xx_PMUXCR_QE(3) | > MPC85xx_PMUXCR_QE(9) | > MPC85xx_PMUXCR_QE(12)); > diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c > index a5d73fabe4d1..78472179b05a 100644 > --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c > +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c > @@ -261,11 +261,11 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) > pxclk = clamp_t(u32, pxclk, 2, 31); > > /* Disable the pixel clock, and set it to non-inverted and no delay */ > - clrbits32(&guts->clkdvdr, > + clrbits32_be(&guts->clkdvdr, > CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); > > /* Enable the clock and set the pxclk */ > - setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); > + setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); > > iounmap(guts); > } > diff --git a/arch/powerpc/platforms/8xx/adder875.c b/arch/powerpc/platforms/8xx/adder875.c > index bcef9f66191e..d21d0b8fd2a7 100644 > --- a/arch/powerpc/platforms/8xx/adder875.c > +++ b/arch/powerpc/platforms/8xx/adder875.c > @@ -77,7 +77,7 @@ static void __init init_ioports(void) > cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); > > /* Set FEC1 and FEC2 to MII mode */ > - clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); > + clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); > } > > static void __init adder875_setup(void) > diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c > index 027c42d8966c..2ed24abd0b40 100644 > --- a/arch/powerpc/platforms/8xx/m8xx_setup.c > +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c > @@ -103,7 +103,7 @@ void __init mpc8xx_calibrate_decr(void) > > /* Force all 8xx processors to use divide by 16 processor clock. */ > clk_r2 = immr_map(im_clkrst); > - setbits32(&clk_r2->car_sccr, 0x02000000); > + setbits32_be(&clk_r2->car_sccr, 0x02000000); > immr_unmap(clk_r2); > > /* Processor frequency is MHz. > @@ -203,7 +203,7 @@ void __noreturn mpc8xx_restart(char *cmd) > > local_irq_disable(); > > - setbits32(&clk_r->car_plprcr, 0x00000080); > + setbits32_be(&clk_r->car_plprcr, 0x00000080); > /* Clear the ME bit in MSR to cause checkstop on machine check > */ > mtmsr(mfmsr() & ~0x1000); > diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c > index 8d02f5ff4481..a25e5ab15d65 100644 > --- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c > +++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c > @@ -87,7 +87,7 @@ static void __init init_ioports(void) > cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX); > > /* Set FEC1 and FEC2 to MII mode */ > - clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); > + clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); > } > > static void __init mpc86xads_setup_arch(void) > @@ -112,7 +112,7 @@ static void __init mpc86xads_setup_arch(void) > return; > } > > - clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN); > + clrbits32_be(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN); > iounmap(bcsr_io); > } > > diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c > index a0c83c1905c6..8aad0fb9090b 100644 > --- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c > +++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c > @@ -123,7 +123,7 @@ static void __init init_ioports(void) > cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX); > > /* Set FEC1 and FEC2 to MII mode */ > - clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); > + clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); > } > > static void __init mpc885ads_setup_arch(void) > @@ -148,33 +148,33 @@ static void __init mpc885ads_setup_arch(void) > return; > } > > - clrbits32(&bcsr[1], BCSR1_RS232EN_1); > + clrbits32_be(&bcsr[1], BCSR1_RS232EN_1); > #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 > - setbits32(&bcsr[1], BCSR1_RS232EN_2); > + setbits32_be(&bcsr[1], BCSR1_RS232EN_2); > #else > - clrbits32(&bcsr[1], BCSR1_RS232EN_2); > + clrbits32_be(&bcsr[1], BCSR1_RS232EN_2); > #endif > > - clrbits32(bcsr5, BCSR5_MII1_EN); > - setbits32(bcsr5, BCSR5_MII1_RST); > + clrbits32_be(bcsr5, BCSR5_MII1_EN); > + setbits32_be(bcsr5, BCSR5_MII1_RST); > udelay(1000); > - clrbits32(bcsr5, BCSR5_MII1_RST); > + clrbits32_be(bcsr5, BCSR5_MII1_RST); > > #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 > - clrbits32(bcsr5, BCSR5_MII2_EN); > - setbits32(bcsr5, BCSR5_MII2_RST); > + clrbits32_be(bcsr5, BCSR5_MII2_EN); > + setbits32_be(bcsr5, BCSR5_MII2_RST); > udelay(1000); > - clrbits32(bcsr5, BCSR5_MII2_RST); > + clrbits32_be(bcsr5, BCSR5_MII2_RST); > #else > - setbits32(bcsr5, BCSR5_MII2_EN); > + setbits32_be(bcsr5, BCSR5_MII2_EN); > #endif > > #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 > - clrbits32(&bcsr[4], BCSR4_ETH10_RST); > + clrbits32_be(&bcsr[4], BCSR4_ETH10_RST); > udelay(1000); > - setbits32(&bcsr[4], BCSR4_ETH10_RST); > + setbits32_be(&bcsr[4], BCSR4_ETH10_RST); > > - setbits32(&bcsr[1], BCSR1_ETHEN); > + setbits32_be(&bcsr[1], BCSR1_ETHEN); > > np = of_find_node_by_path("/soc at ff000000/cpm at 9c0/serial at a80"); > #else > diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c > index db0be007fd06..6df4533aa851 100644 > --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c > +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c > @@ -53,7 +53,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d) > void __iomem *io_base = irq_data_get_irq_chip_data(d); > u32 mask = 1 << irq; > > - clrbits32(io_base + FLIPPER_IMR, mask); > + clrbits32_be(io_base + FLIPPER_IMR, mask); > /* this is at least needed for RSW */ > out_be32(io_base + FLIPPER_ICR, mask); > } > @@ -72,7 +72,7 @@ static void flipper_pic_mask(struct irq_data *d) > int irq = irqd_to_hwirq(d); > void __iomem *io_base = irq_data_get_irq_chip_data(d); > > - clrbits32(io_base + FLIPPER_IMR, 1 << irq); > + clrbits32_be(io_base + FLIPPER_IMR, 1 << irq); > } > > static void flipper_pic_unmask(struct irq_data *d) > @@ -80,7 +80,7 @@ static void flipper_pic_unmask(struct irq_data *d) > int irq = irqd_to_hwirq(d); > void __iomem *io_base = irq_data_get_irq_chip_data(d); > > - setbits32(io_base + FLIPPER_IMR, 1 << irq); > + setbits32_be(io_base + FLIPPER_IMR, 1 << irq); > } > > > diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c > index 8112b39879d6..5487710bed1c 100644 > --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c > +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c > @@ -50,7 +50,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d) > void __iomem *io_base = irq_data_get_irq_chip_data(d); > u32 mask = 1 << irq; > > - clrbits32(io_base + HW_BROADWAY_IMR, mask); > + clrbits32_be(io_base + HW_BROADWAY_IMR, mask); > out_be32(io_base + HW_BROADWAY_ICR, mask); > } > > @@ -67,7 +67,7 @@ static void hlwd_pic_mask(struct irq_data *d) > int irq = irqd_to_hwirq(d); > void __iomem *io_base = irq_data_get_irq_chip_data(d); > > - clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); > + clrbits32_be(io_base + HW_BROADWAY_IMR, 1 << irq); > } > > static void hlwd_pic_unmask(struct irq_data *d) > @@ -75,10 +75,10 @@ static void hlwd_pic_unmask(struct irq_data *d) > int irq = irqd_to_hwirq(d); > void __iomem *io_base = irq_data_get_irq_chip_data(d); > > - setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); > + setbits32_be(io_base + HW_BROADWAY_IMR, 1 << irq); > > /* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */ > - clrbits32(io_base + HW_STARLET_IMR, 1 << irq); > + clrbits32_be(io_base + HW_STARLET_IMR, 1 << irq); > } > > > diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c > index 403523c061ba..dd511e19147a 100644 > --- a/arch/powerpc/platforms/embedded6xx/wii.c > +++ b/arch/powerpc/platforms/embedded6xx/wii.c > @@ -134,7 +134,7 @@ static void __init wii_setup_arch(void) > hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE); > if (hw_gpio) { > /* turn off the front blue led and IR light */ > - clrbits32(hw_gpio + HW_GPIO_OUT(0), > + clrbits32_be(hw_gpio + HW_GPIO_OUT(0), > HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR); > } > } > @@ -145,7 +145,7 @@ static void __noreturn wii_restart(char *cmd) > > if (hw_ctrl) { > /* clear the system reset pin to cause a reset */ > - clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS); > + clrbits32_be(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS); > } > wii_spin(); > } > @@ -159,13 +159,13 @@ static void wii_power_off(void) > * set the owner of the shutdown pin to ARM, because it is > * accessed through the registers for the ARM, below > */ > - clrbits32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN); > + clrbits32_be(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN); > > /* make sure that the poweroff GPIO is configured as output */ > - setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN); > + setbits32_be(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN); > > /* drive the poweroff GPIO high */ > - setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN); > + setbits32_be(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN); > } > wii_spin(); > } > diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c > index 4f8dcf124828..9de5f13c51cb 100644 > --- a/arch/powerpc/sysdev/cpm1.c > +++ b/arch/powerpc/sysdev/cpm1.c > @@ -60,14 +60,14 @@ static void cpm_mask_irq(struct irq_data *d) > { > unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); > > - clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); > + clrbits32_be(&cpic_reg->cpic_cimr, (1 << cpm_vec)); > } > > static void cpm_unmask_irq(struct irq_data *d) > { > unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); > > - setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); > + setbits32_be(&cpic_reg->cpic_cimr, (1 << cpm_vec)); > } > > static void cpm_end_irq(struct irq_data *d) > @@ -188,7 +188,7 @@ unsigned int cpm_pic_init(void) > if (setup_irq(eirq, &cpm_error_irqaction)) > printk(KERN_ERR "Could not allocate CPM error IRQ!"); > > - setbits32(&cpic_reg->cpic_cicr, CICR_IEN); > + setbits32_be(&cpic_reg->cpic_cicr, CICR_IEN); > > end: > of_node_put(np); > @@ -317,14 +317,14 @@ static void cpm1_set_pin32(int port, int pin, int flags) > &mpc8xx_immr->im_cpm.cp_pedir; > > if (flags & CPM_PIN_OUTPUT) > - setbits32(&iop->dir, pin); > + setbits32_be(&iop->dir, pin); > else > - clrbits32(&iop->dir, pin); > + clrbits32_be(&iop->dir, pin); > > if (!(flags & CPM_PIN_GPIO)) > - setbits32(&iop->par, pin); > + setbits32_be(&iop->par, pin); > else > - clrbits32(&iop->par, pin); > + clrbits32_be(&iop->par, pin); > > if (port == CPM_PORTB) { > if (flags & CPM_PIN_OPENDRAIN) > @@ -335,14 +335,14 @@ static void cpm1_set_pin32(int port, int pin, int flags) > > if (port == CPM_PORTE) { > if (flags & CPM_PIN_SECONDARY) > - setbits32(&iop->sor, pin); > + setbits32_be(&iop->sor, pin); > else > - clrbits32(&iop->sor, pin); > + clrbits32_be(&iop->sor, pin); > > if (flags & CPM_PIN_OPENDRAIN) > - setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); > + setbits32_be(&mpc8xx_immr->im_cpm.cp_peodr, pin); > else > - clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); > + clrbits32_be(&mpc8xx_immr->im_cpm.cp_peodr, pin); > } > } > > @@ -732,7 +732,7 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) > > spin_lock_irqsave(&cpm1_gc->lock, flags); > > - setbits32(&iop->dir, pin_mask); > + setbits32_be(&iop->dir, pin_mask); > __cpm1_gpio32_set(mm_gc, pin_mask, val); > > spin_unlock_irqrestore(&cpm1_gc->lock, flags); > @@ -750,7 +750,7 @@ static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) > > spin_lock_irqsave(&cpm1_gc->lock, flags); > > - clrbits32(&iop->dir, pin_mask); > + clrbits32_be(&iop->dir, pin_mask); > > spin_unlock_irqrestore(&cpm1_gc->lock, flags); > > diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c > index 07718b9a2c99..445d6e45a6de 100644 > --- a/arch/powerpc/sysdev/cpm2.c > +++ b/arch/powerpc/sysdev/cpm2.c > @@ -335,22 +335,22 @@ void cpm2_set_pin(int port, int pin, int flags) > pin = 1 << (31 - pin); > > if (flags & CPM_PIN_OUTPUT) > - setbits32(&iop[port].dir, pin); > + setbits32_be(&iop[port].dir, pin); > else > - clrbits32(&iop[port].dir, pin); > + clrbits32_be(&iop[port].dir, pin); > > if (!(flags & CPM_PIN_GPIO)) > - setbits32(&iop[port].par, pin); > + setbits32_be(&iop[port].par, pin); > else > - clrbits32(&iop[port].par, pin); > + clrbits32_be(&iop[port].par, pin); > > if (flags & CPM_PIN_SECONDARY) > - setbits32(&iop[port].sor, pin); > + setbits32_be(&iop[port].sor, pin); > else > - clrbits32(&iop[port].sor, pin); > + clrbits32_be(&iop[port].sor, pin); > > if (flags & CPM_PIN_OPENDRAIN) > - setbits32(&iop[port].odr, pin); > + setbits32_be(&iop[port].odr, pin); > else > - clrbits32(&iop[port].odr, pin); > + clrbits32_be(&iop[port].odr, pin); > } > diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c > index b74508175b67..d36a95708aaf 100644 > --- a/arch/powerpc/sysdev/cpm_common.c > +++ b/arch/powerpc/sysdev/cpm_common.c > @@ -165,7 +165,7 @@ static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) > > spin_lock_irqsave(&cpm2_gc->lock, flags); > > - setbits32(&iop->dir, pin_mask); > + setbits32_be(&iop->dir, pin_mask); > __cpm2_gpio32_set(mm_gc, pin_mask, val); > > spin_unlock_irqrestore(&cpm2_gc->lock, flags); > @@ -183,7 +183,7 @@ static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) > > spin_lock_irqsave(&cpm2_gc->lock, flags); > > - clrbits32(&iop->dir, pin_mask); > + clrbits32_be(&iop->dir, pin_mask); > > spin_unlock_irqrestore(&cpm2_gc->lock, flags); > > diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c > index c27058e5df26..2b7e2b4a2543 100644 > --- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c > +++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c > @@ -124,23 +124,23 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev) > > switch (ways) { > case LOCK_WAYS_EIGHTH: > - setbits32(&l2ctlr->ctl, > + setbits32_be(&l2ctlr->ctl, > L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH); > break; > > case LOCK_WAYS_TWO_EIGHTH: > - setbits32(&l2ctlr->ctl, > + setbits32_be(&l2ctlr->ctl, > L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART); > break; > > case LOCK_WAYS_HALF: > - setbits32(&l2ctlr->ctl, > + setbits32_be(&l2ctlr->ctl, > L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF); > break; > > case LOCK_WAYS_FULL: > default: > - setbits32(&l2ctlr->ctl, > + setbits32_be(&l2ctlr->ctl, > L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL); > break; > } > diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c > index 5340a483cf55..994233e41b91 100644 > --- a/arch/powerpc/sysdev/fsl_lbc.c > +++ b/arch/powerpc/sysdev/fsl_lbc.c > @@ -192,7 +192,7 @@ static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl, > struct fsl_lbc_regs __iomem *lbc = ctrl->regs; > > /* clear event registers */ > - setbits32(&lbc->ltesr, LTESR_CLEAR); > + setbits32_be(&lbc->ltesr, LTESR_CLEAR); > out_be32(&lbc->lteatr, 0); > out_be32(&lbc->ltear, 0); > out_be32(&lbc->lteccr, LTECCR_CLEAR); > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index 918be816b097..17aa5ee63d34 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -1196,11 +1196,11 @@ static int fsl_pci_pme_probe(struct pci_controller *hose) > pci = hose->private_data; > > /* Enable PTOD, ENL23D & EXL23D */ > - clrbits32(&pci->pex_pme_mes_disr, > + clrbits32_be(&pci->pex_pme_mes_disr, > PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); > > out_be32(&pci->pex_pme_mes_ier, 0); > - setbits32(&pci->pex_pme_mes_ier, > + setbits32_be(&pci->pex_pme_mes_ier, > PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); > > /* PME Enable */ > @@ -1218,7 +1218,7 @@ static void send_pme_turnoff_message(struct pci_controller *hose) > int i; > > /* Send PME_Turn_Off Message Request */ > - setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); > + setbits32_be(&pci->pex_pmcr, PEX_PMCR_PTOMR); > > /* Wait trun off done */ > for (i = 0; i < 150; i++) { > @@ -1254,7 +1254,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) > int i; > > /* Send Exit L2 State Message */ > - setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); > + setbits32_be(&pci->pex_pmcr, PEX_PMCR_EXL2S); > > /* Wait exit done */ > for (i = 0; i < 150; i++) { > diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c > index 232225e7f863..bbcf4cb89bb6 100644 > --- a/arch/powerpc/sysdev/fsl_pmc.c > +++ b/arch/powerpc/sysdev/fsl_pmc.c > @@ -37,7 +37,7 @@ static int pmc_suspend_enter(suspend_state_t state) > { > int ret; > > - setbits32(&pmc_regs->pmcsr, PMCSR_SLP); > + setbits32_be(&pmc_regs->pmcsr, PMCSR_SLP); > /* At this point, the CPU is asleep. */ > > /* Upon resume, wait for SLP bit to be clear. */ > diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c > index 9259a94f70e1..bd2a7606bfce 100644 > --- a/arch/powerpc/sysdev/fsl_rcpm.c > +++ b/arch/powerpc/sysdev/fsl_rcpm.c > @@ -33,10 +33,10 @@ static void rcpm_v1_irq_mask(int cpu) > int hw_cpu = get_hard_smp_processor_id(cpu); > unsigned int mask = 1 << hw_cpu; > > - setbits32(&rcpm_v1_regs->cpmimr, mask); > - setbits32(&rcpm_v1_regs->cpmcimr, mask); > - setbits32(&rcpm_v1_regs->cpmmcmr, mask); > - setbits32(&rcpm_v1_regs->cpmnmimr, mask); > + setbits32_be(&rcpm_v1_regs->cpmimr, mask); > + setbits32_be(&rcpm_v1_regs->cpmcimr, mask); > + setbits32_be(&rcpm_v1_regs->cpmmcmr, mask); > + setbits32_be(&rcpm_v1_regs->cpmnmimr, mask); > } > > static void rcpm_v2_irq_mask(int cpu) > @@ -44,10 +44,10 @@ static void rcpm_v2_irq_mask(int cpu) > int hw_cpu = get_hard_smp_processor_id(cpu); > unsigned int mask = 1 << hw_cpu; > > - setbits32(&rcpm_v2_regs->tpmimr0, mask); > - setbits32(&rcpm_v2_regs->tpmcimr0, mask); > - setbits32(&rcpm_v2_regs->tpmmcmr0, mask); > - setbits32(&rcpm_v2_regs->tpmnmimr0, mask); > + setbits32_be(&rcpm_v2_regs->tpmimr0, mask); > + setbits32_be(&rcpm_v2_regs->tpmcimr0, mask); > + setbits32_be(&rcpm_v2_regs->tpmmcmr0, mask); > + setbits32_be(&rcpm_v2_regs->tpmnmimr0, mask); > } > > static void rcpm_v1_irq_unmask(int cpu) > @@ -55,10 +55,10 @@ static void rcpm_v1_irq_unmask(int cpu) > int hw_cpu = get_hard_smp_processor_id(cpu); > unsigned int mask = 1 << hw_cpu; > > - clrbits32(&rcpm_v1_regs->cpmimr, mask); > - clrbits32(&rcpm_v1_regs->cpmcimr, mask); > - clrbits32(&rcpm_v1_regs->cpmmcmr, mask); > - clrbits32(&rcpm_v1_regs->cpmnmimr, mask); > + clrbits32_be(&rcpm_v1_regs->cpmimr, mask); > + clrbits32_be(&rcpm_v1_regs->cpmcimr, mask); > + clrbits32_be(&rcpm_v1_regs->cpmmcmr, mask); > + clrbits32_be(&rcpm_v1_regs->cpmnmimr, mask); > } > > static void rcpm_v2_irq_unmask(int cpu) > @@ -66,26 +66,26 @@ static void rcpm_v2_irq_unmask(int cpu) > int hw_cpu = get_hard_smp_processor_id(cpu); > unsigned int mask = 1 << hw_cpu; > > - clrbits32(&rcpm_v2_regs->tpmimr0, mask); > - clrbits32(&rcpm_v2_regs->tpmcimr0, mask); > - clrbits32(&rcpm_v2_regs->tpmmcmr0, mask); > - clrbits32(&rcpm_v2_regs->tpmnmimr0, mask); > + clrbits32_be(&rcpm_v2_regs->tpmimr0, mask); > + clrbits32_be(&rcpm_v2_regs->tpmcimr0, mask); > + clrbits32_be(&rcpm_v2_regs->tpmmcmr0, mask); > + clrbits32_be(&rcpm_v2_regs->tpmnmimr0, mask); > } > > static void rcpm_v1_set_ip_power(bool enable, u32 mask) > { > if (enable) > - setbits32(&rcpm_v1_regs->ippdexpcr, mask); > + setbits32_be(&rcpm_v1_regs->ippdexpcr, mask); > else > - clrbits32(&rcpm_v1_regs->ippdexpcr, mask); > + clrbits32_be(&rcpm_v1_regs->ippdexpcr, mask); > } > > static void rcpm_v2_set_ip_power(bool enable, u32 mask) > { > if (enable) > - setbits32(&rcpm_v2_regs->ippdexpcr[0], mask); > + setbits32_be(&rcpm_v2_regs->ippdexpcr[0], mask); > else > - clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask); > + clrbits32_be(&rcpm_v2_regs->ippdexpcr[0], mask); > } > > static void rcpm_v1_cpu_enter_state(int cpu, int state) > @@ -95,10 +95,10 @@ static void rcpm_v1_cpu_enter_state(int cpu, int state) > > switch (state) { > case E500_PM_PH10: > - setbits32(&rcpm_v1_regs->cdozcr, mask); > + setbits32_be(&rcpm_v1_regs->cdozcr, mask); > break; > case E500_PM_PH15: > - setbits32(&rcpm_v1_regs->cnapcr, mask); > + setbits32_be(&rcpm_v1_regs->cnapcr, mask); > break; > default: > pr_warn("Unknown cpu PM state (%d)\n", state); > @@ -114,16 +114,16 @@ static void rcpm_v2_cpu_enter_state(int cpu, int state) > switch (state) { > case E500_PM_PH10: > /* one bit corresponds to one thread for PH10 of 6500 */ > - setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu); > + setbits32_be(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu); > break; > case E500_PM_PH15: > - setbits32(&rcpm_v2_regs->pcph15setr, mask); > + setbits32_be(&rcpm_v2_regs->pcph15setr, mask); > break; > case E500_PM_PH20: > - setbits32(&rcpm_v2_regs->pcph20setr, mask); > + setbits32_be(&rcpm_v2_regs->pcph20setr, mask); > break; > case E500_PM_PH30: > - setbits32(&rcpm_v2_regs->pcph30setr, mask); > + setbits32_be(&rcpm_v2_regs->pcph30setr, mask); > break; > default: > pr_warn("Unknown cpu PM state (%d)\n", state); > @@ -172,10 +172,10 @@ static void rcpm_v1_cpu_exit_state(int cpu, int state) > > switch (state) { > case E500_PM_PH10: > - clrbits32(&rcpm_v1_regs->cdozcr, mask); > + clrbits32_be(&rcpm_v1_regs->cdozcr, mask); > break; > case E500_PM_PH15: > - clrbits32(&rcpm_v1_regs->cnapcr, mask); > + clrbits32_be(&rcpm_v1_regs->cnapcr, mask); > break; > default: > pr_warn("Unknown cpu PM state (%d)\n", state); > @@ -196,16 +196,16 @@ static void rcpm_v2_cpu_exit_state(int cpu, int state) > > switch (state) { > case E500_PM_PH10: > - setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu); > + setbits32_be(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu); > break; > case E500_PM_PH15: > - setbits32(&rcpm_v2_regs->pcph15clrr, mask); > + setbits32_be(&rcpm_v2_regs->pcph15clrr, mask); > break; > case E500_PM_PH20: > - setbits32(&rcpm_v2_regs->pcph20clrr, mask); > + setbits32_be(&rcpm_v2_regs->pcph20clrr, mask); > break; > case E500_PM_PH30: > - setbits32(&rcpm_v2_regs->pcph30clrr, mask); > + setbits32_be(&rcpm_v2_regs->pcph30clrr, mask); > break; > default: > pr_warn("Unknown cpu PM state (%d)\n", state); > @@ -226,7 +226,7 @@ static int rcpm_v1_plat_enter_state(int state) > > switch (state) { > case PLAT_PM_SLEEP: > - setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP); > + setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_SLP); > > /* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */ > result = spin_event_timeout( > @@ -253,9 +253,9 @@ static int rcpm_v2_plat_enter_state(int state) > switch (state) { > case PLAT_PM_LPM20: > /* clear previous LPM20 status */ > - setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST); > + setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST); > /* enter LPM20 status */ > - setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ); > + setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ); > > /* At this point, the device is in LPM20 status. */ > > @@ -291,9 +291,9 @@ static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze) > > if (freeze) { > mask = in_be32(tben_reg); > - clrbits32(tben_reg, mask); > + clrbits32_be(tben_reg, mask); > } else { > - setbits32(tben_reg, mask); > + setbits32_be(tben_reg, mask); > } > > /* read back to push the previous write */ > diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c > index 5011ffea4e4b..278e63cc8afe 100644 > --- a/arch/powerpc/sysdev/fsl_rio.c > +++ b/arch/powerpc/sysdev/fsl_rio.c > @@ -668,10 +668,10 @@ int fsl_rio_setup(struct platform_device *dev) > out_be32(priv->regs_win > + RIO_CCSR + i*0x20, 0); > /* Set 1x lane */ > - setbits32(priv->regs_win > + setbits32_be(priv->regs_win > + RIO_CCSR + i*0x20, 0x02000000); > /* Enable ports */ > - setbits32(priv->regs_win > + setbits32_be(priv->regs_win > + RIO_CCSR + i*0x20, 0x00600000); > msleep(100); > if (in_be32((priv->regs_win > diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c > index 88b35a3dcdc5..134ba53f0fcb 100644 > --- a/arch/powerpc/sysdev/fsl_rmu.c > +++ b/arch/powerpc/sysdev/fsl_rmu.c > @@ -355,7 +355,7 @@ fsl_rio_dbell_handler(int irq, void *dev_instance) > dmsg->sid, dmsg->tid, > dmsg->info); > } > - setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); > + setbits32_be(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); > out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); > } > > @@ -909,10 +909,10 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) > out_be32(&rmu->msg_regs->imr, 0x001b0060); > > /* Set number of queue entries */ > - setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); > + setbits32_be(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); > > /* Now enable the unit */ > - setbits32(&rmu->msg_regs->imr, 0x1); > + setbits32_be(&rmu->msg_regs->imr, 0x1); > > out: > return rc; > @@ -1015,7 +1015,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox) > rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; > > out1: > - setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); > + setbits32_be(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); > > out2: > return buf; > diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c > index 87e7c42777a8..70b02ba90220 100644 > --- a/arch/powerpc/sysdev/mpic_timer.c > +++ b/arch/powerpc/sysdev/mpic_timer.c > @@ -154,7 +154,7 @@ static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks, > > tcr = casc_priv->tcr_value | > (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET); > - setbits32(priv->group_tcr, tcr); > + setbits32_be(priv->group_tcr, tcr); > > tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks); > > @@ -253,7 +253,7 @@ void mpic_start_timer(struct mpic_timer *handle) > struct timer_group_priv *priv = container_of(handle, > struct timer_group_priv, timer[handle->num]); > > - clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); > + clrbits32_be(&priv->regs[handle->num].gtbcr, TIMER_STOP); > } > EXPORT_SYMBOL(mpic_start_timer); > > @@ -269,7 +269,7 @@ void mpic_stop_timer(struct mpic_timer *handle) > struct timer_group_priv, timer[handle->num]); > struct cascade_priv *casc_priv; > > - setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); > + setbits32_be(&priv->regs[handle->num].gtbcr, TIMER_STOP); > > casc_priv = priv->timer[handle->num].cascade_handle; > if (casc_priv) { > @@ -340,7 +340,7 @@ void mpic_free_timer(struct mpic_timer *handle) > u32 tcr; > tcr = casc_priv->tcr_value | (casc_priv->tcr_value << > MPIC_TIMER_TCR_ROVR_OFFSET); > - clrbits32(priv->group_tcr, tcr); > + clrbits32_be(priv->group_tcr, tcr); > priv->idle |= casc_priv->cascade_map; > priv->timer[handle->num].cascade_handle = NULL; > } else { > @@ -508,7 +508,7 @@ static void timer_group_init(struct device_node *np) > > /* Init FSL timer hardware */ > if (priv->flags & FSL_GLOBAL_TIMER) > - setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); > + setbits32_be(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); > > list_add_tail(&priv->node, &timer_group_list); > > @@ -531,7 +531,7 @@ static void mpic_timer_resume(void) > list_for_each_entry(priv, &timer_group_list, node) { > /* Init FSL timer hardware */ > if (priv->flags & FSL_GLOBAL_TIMER) > - setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); > + setbits32_be(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); > } > } > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be 2018-09-10 5:16 ` Christophe LEROY @ 2018-09-10 18:50 ` LABBE Corentin 0 siblings, 0 replies; 15+ messages in thread From: LABBE Corentin @ 2018-09-10 18:50 UTC (permalink / raw) To: linux-arm-kernel On Mon, Sep 10, 2018 at 07:16:56AM +0200, Christophe LEROY wrote: > > > Le 07/09/2018 ? 21:41, Corentin Labbe a ?crit?: > > Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on > > the used data type. > > Wouldn't it be better to call them setbits_be32() / clrbits_be32() to > have something looking similar to in_be32() / ou_be32() ? > I agree, I will update the patch. Thanks ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe 2018-09-07 19:41 ` [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be Corentin Labbe @ 2018-09-07 19:41 ` Corentin Labbe 2018-09-07 20:00 ` Scott Wood 2018-09-10 5:22 ` Christophe LEROY 2018-09-07 19:41 ` [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch Corentin Labbe ` (4 subsequent siblings) 6 siblings, 2 replies; 15+ messages in thread From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw) To: linux-arm-kernel This patch adds setbits32/clrbits32/clrsetbits32 and setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. Signed-off-by: Corentin Labbe <clabbe@baylibre.com> --- include/linux/setbits.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 include/linux/setbits.h diff --git a/include/linux/setbits.h b/include/linux/setbits.h new file mode 100644 index 000000000000..3e1e273551bb --- /dev/null +++ b/include/linux/setbits.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SETBITS_H +#define __LINUX_SETBITS_H + +#include <linux/io.h> + +#define __setbits(readfunction, writefunction, addr, set) \ + writefunction((readfunction(addr) | (set)), addr) +#define __clrbits(readfunction, writefunction, addr, mask) \ + writefunction((readfunction(addr) & ~(mask)), addr) +#define __clrsetbits(readfunction, writefunction, addr, mask, set) \ + writefunction(((readfunction(addr) & ~(mask)) | (set)), addr) +#define __setclrbits(readfunction, writefunction, addr, mask, set) \ + writefunction(((readfunction(addr) | (seti)) & ~(mask)), addr) + +#define setbits32(addr, set) __setbits(readl, writel, addr, set) +#define setbits32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \ + addr, set) + +#define clrbits32(addr, mask) __clrbits(readl, writel, addr, mask) +#define clrbits32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \ + addr, mask) + +#define clrsetbits32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set) +#define clrsetbits32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) + +#define setclrbits32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set) +#define setclrbits32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ + writel_relaxed, \ + addr, mask, set) + +/* We cannot use CONFIG_64BIT as some x86 drivers use writeq */ +#if defined(writeq) && defined(readq) +#define setbits64(addr, set) __setbits(readq, writeq, addr, set) +#define setbits64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \ + addr, set) + +#define clrbits64(addr, mask) __clrbits(readq, writeq, addr, mask) +#define clrbits64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \ + addr, mask) + +#define clrsetbits64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set) +#define clrsetbits64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) + +#define setclrbits64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set) +#define setclrbits64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \ + writeq_relaxed, \ + addr, mask, set) +#endif /* writeq/readq */ + +#endif /* __LINUX_SETBITS_H */ -- 2.16.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h 2018-09-07 19:41 ` [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h Corentin Labbe @ 2018-09-07 20:00 ` Scott Wood 2018-09-10 18:49 ` LABBE Corentin 2018-09-10 5:22 ` Christophe LEROY 1 sibling, 1 reply; 15+ messages in thread From: Scott Wood @ 2018-09-07 20:00 UTC (permalink / raw) To: linux-arm-kernel On Fri, 2018-09-07 at 19:41 +0000, Corentin Labbe wrote: > This patch adds setbits32/clrbits32/clrsetbits32 and > setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. > > Signed-off-by: Corentin Labbe <clabbe@baylibre.com> > --- > include/linux/setbits.h | 55 > +++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 include/linux/setbits.h > > diff --git a/include/linux/setbits.h b/include/linux/setbits.h > new file mode 100644 > index 000000000000..3e1e273551bb > --- /dev/null > +++ b/include/linux/setbits.h > @@ -0,0 +1,55 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __LINUX_SETBITS_H > +#define __LINUX_SETBITS_H > + > +#include <linux/io.h> > + > +#define __setbits(readfunction, writefunction, addr, set) \ > + writefunction((readfunction(addr) | (set)), addr) > +#define __clrbits(readfunction, writefunction, addr, mask) \ > + writefunction((readfunction(addr) & ~(mask)), addr) > +#define __clrsetbits(readfunction, writefunction, addr, mask, set) \ > + writefunction(((readfunction(addr) & ~(mask)) | (set)), addr) > +#define __setclrbits(readfunction, writefunction, addr, mask, set) \ > + writefunction(((readfunction(addr) | (seti)) & ~(mask)), addr) > + > +#define setbits32(addr, set) __setbits(readl, writel, addr, set) > +#define setbits32_relaxed(addr, set) __setbits(readl_relaxed, > writel_relaxed, \ > + addr, set) > + > +#define clrbits32(addr, mask) __clrbits(readl, writel, addr, mask) > +#define clrbits32_relaxed(addr, mask) __clrbits(readl_relaxed, > writel_relaxed, \ > + addr, mask) So now setbits32/clrbits32 is implicitly little-endian? Introducing new implicit-endian accessors is probably a bad thing in general, but doing it with a name that until this patchset was implicitly big-endian (at least on powerpc) seems worse. Why not setbits32_le()? > + > +#define clrsetbits32(addr, mask, set) __clrsetbits(readl, writel, addr, > mask, set) > +#define clrsetbits32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ > + writel_relaxed, > \ > + addr, mask, set) > + > +#define setclrbits32(addr, mask, set) __setclrbits(readl, writel, addr, > mask, set) > +#define setclrbits32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ > + writel_relaxed, > \ > + addr, mask, set) What's the use case for setclrbits? I don't see it used anywhere in this patchset (not even in the coccinelle patterns), it doesn't seem like it would be a common pattern, and it could easily get confused with clrsetbits. -Scott ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h 2018-09-07 20:00 ` Scott Wood @ 2018-09-10 18:49 ` LABBE Corentin 0 siblings, 0 replies; 15+ messages in thread From: LABBE Corentin @ 2018-09-10 18:49 UTC (permalink / raw) To: linux-arm-kernel On Fri, Sep 07, 2018 at 03:00:40PM -0500, Scott Wood wrote: > On Fri, 2018-09-07 at 19:41 +0000, Corentin Labbe wrote: > > This patch adds setbits32/clrbits32/clrsetbits32 and > > setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. > > > > Signed-off-by: Corentin Labbe <clabbe@baylibre.com> > > --- > > include/linux/setbits.h | 55 > > +++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > create mode 100644 include/linux/setbits.h > > > > diff --git a/include/linux/setbits.h b/include/linux/setbits.h > > new file mode 100644 > > index 000000000000..3e1e273551bb > > --- /dev/null > > +++ b/include/linux/setbits.h > > @@ -0,0 +1,55 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef __LINUX_SETBITS_H > > +#define __LINUX_SETBITS_H > > + > > +#include <linux/io.h> > > + > > +#define __setbits(readfunction, writefunction, addr, set) \ > > + writefunction((readfunction(addr) | (set)), addr) > > +#define __clrbits(readfunction, writefunction, addr, mask) \ > > + writefunction((readfunction(addr) & ~(mask)), addr) > > +#define __clrsetbits(readfunction, writefunction, addr, mask, set) \ > > + writefunction(((readfunction(addr) & ~(mask)) | (set)), addr) > > +#define __setclrbits(readfunction, writefunction, addr, mask, set) \ > > + writefunction(((readfunction(addr) | (seti)) & ~(mask)), addr) > > + > > +#define setbits32(addr, set) __setbits(readl, writel, addr, set) > > +#define setbits32_relaxed(addr, set) __setbits(readl_relaxed, > > writel_relaxed, \ > > + addr, set) > > + > > +#define clrbits32(addr, mask) __clrbits(readl, writel, addr, mask) > > +#define clrbits32_relaxed(addr, mask) __clrbits(readl_relaxed, > > writel_relaxed, \ > > + addr, mask) > > So now setbits32/clrbits32 is implicitly little-endian? Introducing new > implicit-endian accessors is probably a bad thing in general, but doing it > with a name that until this patchset was implicitly big-endian (at least on > powerpc) seems worse. Why not setbits32_le()? > I believed that writel/readl was endian agnostic, but It seems that I was wrong. So I will use _le32. > > > + > > +#define clrsetbits32(addr, mask, set) __clrsetbits(readl, writel, addr, > > mask, set) > > +#define clrsetbits32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ > > + writel_relaxed, > > \ > > + addr, mask, set) > > + > > +#define setclrbits32(addr, mask, set) __setclrbits(readl, writel, addr, > > mask, set) > > +#define setclrbits32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ > > + writel_relaxed, > > \ > > + addr, mask, set) > > What's the use case for setclrbits? I don't see it used anywhere in this > patchset (not even in the coccinelle patterns), it doesn't seem like it would > be a common pattern, and it could easily get confused with clrsetbits. > It is absent from the coccinelle script due to copy/paste error. And absent from patchset since it is only two possible example that I can test. If you run the next fixed coccinelle script, you will find some setclrbits. Since I fear that mask and set could have some common bits sometimes, I prefer to keep separate clrsetbits and setclrbits. Regards ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h 2018-09-07 19:41 ` [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h Corentin Labbe 2018-09-07 20:00 ` Scott Wood @ 2018-09-10 5:22 ` Christophe LEROY 2018-09-10 18:53 ` LABBE Corentin 1 sibling, 1 reply; 15+ messages in thread From: Christophe LEROY @ 2018-09-10 5:22 UTC (permalink / raw) To: linux-arm-kernel Le 07/09/2018 ? 21:41, Corentin Labbe a ?crit?: > This patch adds setbits32/clrbits32/clrsetbits32 and > setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. So you changed the name of setbits32() ... to setbits32_be() and now you are adding new functions called setbits32() ... which do something different ? What will happen if any file has been forgotten during the conversion, or if anybody has outoftree drivers and missed this change ? They will silently successfully compile without any error or warning, and the result will be crap buggy. And why would it be more legitim to have setbits32() be implicitely LE instead of implicitely BE ? I really think those new functions should be called something like setbits_le32() ... Christophe > > Signed-off-by: Corentin Labbe <clabbe@baylibre.com> > --- > include/linux/setbits.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 include/linux/setbits.h > > diff --git a/include/linux/setbits.h b/include/linux/setbits.h > new file mode 100644 > index 000000000000..3e1e273551bb > --- /dev/null > +++ b/include/linux/setbits.h > @@ -0,0 +1,55 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __LINUX_SETBITS_H > +#define __LINUX_SETBITS_H > + > +#include <linux/io.h> > + > +#define __setbits(readfunction, writefunction, addr, set) \ > + writefunction((readfunction(addr) | (set)), addr) > +#define __clrbits(readfunction, writefunction, addr, mask) \ > + writefunction((readfunction(addr) & ~(mask)), addr) > +#define __clrsetbits(readfunction, writefunction, addr, mask, set) \ > + writefunction(((readfunction(addr) & ~(mask)) | (set)), addr) > +#define __setclrbits(readfunction, writefunction, addr, mask, set) \ > + writefunction(((readfunction(addr) | (seti)) & ~(mask)), addr) > + > +#define setbits32(addr, set) __setbits(readl, writel, addr, set) > +#define setbits32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \ > + addr, set) > + > +#define clrbits32(addr, mask) __clrbits(readl, writel, addr, mask) > +#define clrbits32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \ > + addr, mask) > + > +#define clrsetbits32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set) > +#define clrsetbits32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \ > + writel_relaxed, \ > + addr, mask, set) > + > +#define setclrbits32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set) > +#define setclrbits32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \ > + writel_relaxed, \ > + addr, mask, set) > + > +/* We cannot use CONFIG_64BIT as some x86 drivers use writeq */ > +#if defined(writeq) && defined(readq) > +#define setbits64(addr, set) __setbits(readq, writeq, addr, set) > +#define setbits64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \ > + addr, set) > + > +#define clrbits64(addr, mask) __clrbits(readq, writeq, addr, mask) > +#define clrbits64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \ > + addr, mask) > + > +#define clrsetbits64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set) > +#define clrsetbits64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \ > + writeq_relaxed, \ > + addr, mask, set) > + > +#define setclrbits64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set) > +#define setclrbits64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \ > + writeq_relaxed, \ > + addr, mask, set) > +#endif /* writeq/readq */ > + > +#endif /* __LINUX_SETBITS_H */ > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h 2018-09-10 5:22 ` Christophe LEROY @ 2018-09-10 18:53 ` LABBE Corentin 0 siblings, 0 replies; 15+ messages in thread From: LABBE Corentin @ 2018-09-10 18:53 UTC (permalink / raw) To: linux-arm-kernel On Mon, Sep 10, 2018 at 07:22:04AM +0200, Christophe LEROY wrote: > > > Le 07/09/2018 ? 21:41, Corentin Labbe a ?crit?: > > This patch adds setbits32/clrbits32/clrsetbits32 and > > setbits64/clrbits64/clrsetbits64 in linux/setbits.h header. > > So you changed the name of setbits32() ... to setbits32_be() and now you > are adding new functions called setbits32() ... which do something > different ? > > What will happen if any file has been forgotten during the conversion, > or if anybody has outoftree drivers and missed this change ? > They will silently successfully compile without any error or warning, > and the result will be crap buggy. > > And why would it be more legitim to have setbits32() be implicitely LE > instead of implicitely BE ? > > I really think those new functions should be called something like > setbits_le32() ... > I believed that writel/readl was endian agnostic so it explain my mistake. I will use xxxbits_le32 as you requests. Thanks Regards ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe 2018-09-07 19:41 ` [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be Corentin Labbe 2018-09-07 19:41 ` [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h Corentin Labbe @ 2018-09-07 19:41 ` Corentin Labbe 2018-09-09 11:13 ` SF Markus Elfring 2018-09-07 19:41 ` [PATCH 4/5] net: ethernet: stmmac: use xxxsetbits32 Corentin Labbe ` (3 subsequent siblings) 6 siblings, 1 reply; 15+ messages in thread From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw) To: linux-arm-kernel This patch add a spatch which convert all open coded of setbits32/clrbits32/clrsetbits32 and their 64 bits counterparts. Signed-off-by: Corentin Labbe <clabbe@baylibre.com> --- scripts/coccinelle/misc/setbits.cocci | 423 ++++++++++++++++++++++++++++++++++ 1 file changed, 423 insertions(+) create mode 100644 scripts/coccinelle/misc/setbits.cocci diff --git a/scripts/coccinelle/misc/setbits.cocci b/scripts/coccinelle/misc/setbits.cocci new file mode 100644 index 000000000000..c01ab6d75eb4 --- /dev/null +++ b/scripts/coccinelle/misc/setbits.cocci @@ -0,0 +1,423 @@ +virtual context + + at pclrsetbits32a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr &= ~clear; +- rr |= set; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + + at pclrsetbits32b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr |= set; +- rr &= ~clear; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + + at pclrbits32@ +identifier rr; +expression reg; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr &= ~clear; +- writel(rr, reg); ++ clrbits32(reg, clear); + + at psetbits32@ +identifier rr; +expression reg; +expression set; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr |= set; +- writel(rr, reg); ++ setbits32(reg, set); + + at psetbits32b@ +identifier rr; +expression reg; +expression set1; +expression set2; +@@ + + u32 rr; + ... +- rr = readl(reg); +- rr |= set1; +- rr |= set2; +- writel(rr, reg); ++ setbits32(reg, set1 | set2); + + at pclrsetbits64a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr &= ~clear; +- rr |= set; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + + at pclrsetbits64b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr |= set; +- rr &= ~clear; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + + at pclrbits64@ +identifier rr; +expression reg; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr &= ~clear; +- writeq(rr, reg); ++ clrbits64(reg, clear); + + at psetbits64@ +identifier rr; +expression reg; +expression set; +@@ + + u64 rr; + ... +- rr = readq(reg); +- rr |= set; +- writeq(rr, reg); ++ setbits64(reg, set); + +@@ +expression dwmac; +expression reg; +expression mask; +expression value; +@@ + +- meson8b_dwmac_mask_bits(dwmac, reg, mask, value); ++ clrsetbits32(dwmac->regs + reg, mask, value); + + at ppclrsetbits32a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u32 rr = readl(reg); +- rr &= ~clear; +- rr |= set; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + + at ppclrsetbits32b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u32 rr = readl(reg); +- rr |= set; +- rr &= ~clear; +- writel(rr, reg); ++ clrsetbits32(reg, clear, set); + + at ppclrbits32@ +identifier rr; +expression reg; +expression clear; +@@ + +- u32 rr = readl(reg); +- rr &= ~clear; +- writel(rr, reg); ++ clrbits32(reg, clear); + + at ppsetbits32@ +identifier rr; +expression reg; +expression set; +@@ + +- u32 rr = readl(reg); +- rr |= set; +- writel(rr, reg); ++ setbits32(reg, set); + + at ppclrsetbits64a@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u64 rr = readq(reg); +- rr &= ~clear; +- rr |= set; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + + at ppclrsetbits64b@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + +- u64 rr = readq(reg); +- rr |= set; +- rr &= ~clear; +- writeq(rr, reg); ++ clrsetbits64(reg, clear, set); + + at ppclrbits64@ +identifier rr; +expression reg; +expression clear; +@@ + +- u64 rr = readq(reg); +- rr &= ~clear; +- writeq(rr, reg); ++ clrbits64(reg, clear); + + at ppsetbits64@ +identifier rr; +expression reg; +expression set; +@@ + +- u64 rr = readq(reg); +- rr |= set; +- writeq(rr, reg); ++ setbits64(reg, set); + + at pif_set_clr@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); + if (...) +- rr |= set; ++ setbits32(reg, set); + else +- rr &= ~clear; ++ clrbits32(reg, clear); +- writel(rr, reg); + + at pifclrset@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u32 rr; + ... +- rr = readl(reg); + if (...) +- rr &= ~clear; ++ clrbits32(reg, clear); + else +- rr |= set; ++ setbits32(reg, set); +- writel(rr, reg); + + at pif_set_clr64@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); + if (...) +- rr |= set; ++ setbits64(reg, set); + else +- rr &= ~clear; ++ clrbits64(reg, clear); +- writeq(rr, reg); + + at pif_clr_set64@ +identifier rr; +expression reg; +expression set; +expression clear; +@@ + + u64 rr; + ... +- rr = readq(reg); + if (...) +- rr &= ~clear; ++ clrbits64(reg, clear); + else +- rr |= set; ++ setbits32(reg, set); +- writeq(rr, reg); + + + at p_setbits32_m2@ +identifier rr; +expression reg; +expression set; +@@ + + u32 rr; + ... +- rr = readl(reg); +- writel(rr | set, reg); ++ setbits32(reg, set); + + at p_clrbits32_m2@ +identifier rr; +expression reg; +expression mask; +@@ + + u32 rr; + ... +- rr = readl(reg); +- writel(rr & ~mask, reg); ++ clrbits32(reg, mask); + + + at p_setbits_oneliner@ +expression addr; +expression set; +@@ +- writel(readl(addr) | set, addr); ++ setbits32(addr, set); + + at p_clrbits_oneliner@ +expression addr; +expression mask; +@@ +- writel(readl(addr) & ~mask, addr); ++ clrbits32(addr, mask); + + at p_clrsetbits_oneliner_a@ +expression addr; +expression set; +expression mask; +@@ +- writel(readl(addr) | set & ~mask, addr); ++ clrsetbits32(addr, mask, set); + + at p_clrsetbits_oneliner_b@ +expression addr; +expression set; +expression mask; +@@ +- writel(readl(addr) & ~mask | set, addr); ++ clrsetbits32(addr, mask, set); + + at p_clrsetbits_oneliner_a2@ +expression addr; +expression set; +expression mask; +@@ +- writel((readl(addr) | set) & ~mask, addr); ++ clrsetbits32(addr, mask, set); + + at p_clrsetbits_oneliner_b2@ +expression addr; +expression set; +expression mask; +@@ +- writel((readl(addr) & ~mask) | set, addr); ++ clrsetbits32(addr, mask, set); + + + + + + + + + + + +// sub optimal way to add header + at header1 depends on psetbits32 || pclrbits32 || pclrsetbits32a || pclrsetbits32b || psetbits64 || pclrbits64 || pclrsetbits64a || pclrsetbits64b || ppsetbits32 || ppclrbits32 || ppclrsetbits32a || ppclrsetbits32b || ppsetbits64 || ppclrbits64 || ppclrsetbits64a || ppclrsetbits64b@ +@@ + #include <linux/io.h> ++ #include <linux/setbits.h> + + at header2 depends on (psetbits32 || pclrbits32 || pclrsetbits32a || pclrsetbits32b || psetbits64 || pclrbits64 || pclrsetbits64a || pclrsetbits64b || ppsetbits32 || ppclrbits32 || ppclrsetbits32a || ppclrsetbits32b || ppsetbits64 || ppclrbits64 || ppclrsetbits64a || ppclrsetbits64b) && !header1@ +@@ + #include <linux/interrupt.h> ++ #include <linux/setbits.h> + + at header3 depends on (psetbits32 || pclrbits32 || pclrsetbits32a || pclrsetbits32b || psetbits64 || pclrbits64 || pclrsetbits64a || pclrsetbits64b || ppsetbits32 || ppclrbits32 || ppclrsetbits32a || ppclrsetbits32b || ppsetbits64 || ppclrbits64 || ppclrsetbits64a || ppclrsetbits64b) && !header2@ +@@ + #include <linux/of.h> ++ #include <linux/setbits.h> + +@@ +expression base; +expression offset; +expression value; +@@ + +- mtu3_setbits(base, offset, value); ++ setbits32(base + offset, value); + +@@ +expression base; +expression offset; +expression mask; +@@ + +- mtu3_clrbits(base, offset, mask); ++ clrbits32(base + offset, mask); + -- 2.16.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch 2018-09-07 19:41 ` [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch Corentin Labbe @ 2018-09-09 11:13 ` SF Markus Elfring 0 siblings, 0 replies; 15+ messages in thread From: SF Markus Elfring @ 2018-09-09 11:13 UTC (permalink / raw) To: linux-arm-kernel How do you think about to add any more meta-data for this semantic patch script? * SPDX identifier * Copyright information * Confidence level https://bottest.wiki.kernel.org/coccicheck > +virtual context Further variables will be needed if you would like to use corresponding operation modes (besides ?patch?). > +expression reg; > +expression set; > +expression clear; I propose once more to avoid the repetition of (unnecessary) SmPL code. This part could be written like the following instead. +expression clear, set, reg; If you would increase the usage of SmPL disjunctions, the specification of duplicate SmPL code could be reduced considerably. * Would you like to merge SmPL rules based on the distinction between the data types ?u32? and ?u64?? * Did you identify any optional code in this transformation approach? > +@@ > +expression base; > +expression offset; > +expression value; > +@@ > + > +- mtu3_setbits(base, offset, value); > ++ setbits32(base + offset, value); > + > +@@ > +expression base; > +expression offset; > +expression mask; > +@@ > + > +- mtu3_clrbits(base, offset, mask); > ++ clrbits32(base + offset, mask); Another update suggestion: + at replacement@ +expression base, offset; +@@ +( +-mtu3_clrbits ++clrbits32 +| +-mtu3_setbits ++setbits32 +)(base +- , ++ + + offset, ...); Would you like to try further software fine-tuning out? Regards, Markus ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/5] net: ethernet: stmmac: use xxxsetbits32 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe ` (2 preceding siblings ...) 2018-09-07 19:41 ` [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch Corentin Labbe @ 2018-09-07 19:41 ` Corentin Labbe 2018-09-07 19:41 ` [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions Corentin Labbe ` (2 subsequent siblings) 6 siblings, 0 replies; 15+ messages in thread From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw) To: linux-arm-kernel This patch convert stmmac driver to use all xxxsetbits32 functions. Signed-off-by: Corentin Labbe <clabbe@baylibre.com> --- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 54 +++++++---------- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 55 ++++------------- .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 21 +++---- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 51 ++++++---------- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 13 ++-- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 42 +++---------- drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 11 +--- drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 17 ++---- .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 30 ++++------ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 69 +++++----------------- .../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 11 +--- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 7 +-- 12 files changed, 108 insertions(+), 273 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index c5979569fd60..035a2ab7b479 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -22,6 +22,7 @@ #include <linux/of_net.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> +#include <linux/setbits.h> #include <linux/stmmac.h> #include "stmmac_platform.h" @@ -75,18 +76,6 @@ struct meson8b_dwmac_clk_configs { struct clk_gate rgmii_tx_en; }; -static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, - u32 mask, u32 value) -{ - u32 data; - - data = readl(dwmac->regs + reg); - data &= ~mask; - data |= (value & mask); - - writel(data, dwmac->regs + reg); -} - static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, const char *name_suffix, const char **parent_names, @@ -192,14 +181,12 @@ static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: /* enable RGMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, - PRG_ETH0_RGMII_MODE, - PRG_ETH0_RGMII_MODE); + clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE, + PRG_ETH0_RGMII_MODE); break; case PHY_INTERFACE_MODE_RMII: /* disable RGMII mode -> enables RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, - PRG_ETH0_RGMII_MODE, 0); + clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE, 0); break; default: dev_err(dwmac->dev, "fail to set phy-mode %s\n", @@ -218,15 +205,15 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: /* enable RGMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, - PRG_ETH0_EXT_PHY_MODE_MASK, - PRG_ETH0_EXT_RGMII_MODE); + clrsetbits32(dwmac->regs + PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RGMII_MODE); break; case PHY_INTERFACE_MODE_RMII: /* disable RGMII mode -> enables RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, - PRG_ETH0_EXT_PHY_MODE_MASK, - PRG_ETH0_EXT_RMII_MODE); + clrsetbits32(dwmac->regs + PRG_ETH0, + PRG_ETH0_EXT_PHY_MODE_MASK, + PRG_ETH0_EXT_RMII_MODE); break; default: dev_err(dwmac->dev, "fail to set phy-mode %s\n", @@ -255,11 +242,11 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_TXID: /* only relevant for RMII mode -> disable in RGMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, - PRG_ETH0_INVERTED_RMII_CLK, 0); + clrsetbits32(dwmac->regs + PRG_ETH0, + PRG_ETH0_INVERTED_RMII_CLK, 0); - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, - tx_dly_val << PRG_ETH0_TXDLY_SHIFT); + clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK, + tx_dly_val << PRG_ETH0_TXDLY_SHIFT); /* Configure the 125MHz RGMII TX clock, the IP block changes * the output automatically (= without us having to configure @@ -287,13 +274,12 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) case PHY_INTERFACE_MODE_RMII: /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, - PRG_ETH0_INVERTED_RMII_CLK, - PRG_ETH0_INVERTED_RMII_CLK); + clrsetbits32(dwmac->regs + PRG_ETH0, + PRG_ETH0_INVERTED_RMII_CLK, + PRG_ETH0_INVERTED_RMII_CLK); /* TX clock delay cannot be configured in RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, - 0); + clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK, 0); break; @@ -304,8 +290,8 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) } /* enable TX_CLK and PHY_REF_CLK generator */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, - PRG_ETH0_TX_AND_PHY_REF_CLK); + clrsetbits32(dwmac->regs + PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, + PRG_ETH0_TX_AND_PHY_REF_CLK); return 0; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 0f660af01a4b..3c7f531feadf 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -27,6 +27,7 @@ #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/regmap.h> +#include <linux/setbits.h> #include <linux/stmmac.h> #include "stmmac.h" @@ -342,50 +343,27 @@ static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) { - u32 v; - - v = readl(ioaddr + EMAC_TX_CTL1); - v |= EMAC_TX_DMA_START; - v |= EMAC_TX_DMA_EN; - writel(v, ioaddr + EMAC_TX_CTL1); + setbits32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_START | EMAC_TX_DMA_EN); } static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) { - u32 v; - - v = readl(ioaddr + EMAC_TX_CTL1); - v |= EMAC_TX_DMA_START; - v |= EMAC_TX_DMA_EN; - writel(v, ioaddr + EMAC_TX_CTL1); + setbits32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_START | EMAC_TX_DMA_EN); } static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) { - u32 v; - - v = readl(ioaddr + EMAC_TX_CTL1); - v &= ~EMAC_TX_DMA_EN; - writel(v, ioaddr + EMAC_TX_CTL1); + clrbits32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_EN); } static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) { - u32 v; - - v = readl(ioaddr + EMAC_RX_CTL1); - v |= EMAC_RX_DMA_START; - v |= EMAC_RX_DMA_EN; - writel(v, ioaddr + EMAC_RX_CTL1); + setbits32(ioaddr + EMAC_RX_CTL1, EMAC_RX_DMA_START | EMAC_RX_DMA_EN); } static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) { - u32 v; - - v = readl(ioaddr + EMAC_RX_CTL1); - v &= ~EMAC_RX_DMA_EN; - writel(v, ioaddr + EMAC_RX_CTL1); + clrbits32(ioaddr + EMAC_RX_CTL1, EMAC_RX_DMA_EN); } static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, @@ -608,11 +586,8 @@ static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) { void __iomem *ioaddr = hw->pcsr; - u32 v; - v = readl(ioaddr + EMAC_RX_CTL0); - v |= EMAC_RX_DO_CRC; - writel(v, ioaddr + EMAC_RX_CTL0); + setbits32(ioaddr + EMAC_RX_CTL0, EMAC_RX_DO_CRC); return 1; } @@ -662,21 +637,16 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, unsigned int pause_time, u32 tx_cnt) { void __iomem *ioaddr = hw->pcsr; - u32 v; - v = readl(ioaddr + EMAC_RX_CTL0); if (fc == FLOW_AUTO) - v |= EMAC_RX_FLOW_CTL_EN; + setbits32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN); else - v &= ~EMAC_RX_FLOW_CTL_EN; - writel(v, ioaddr + EMAC_RX_CTL0); + clrbits32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN); - v = readl(ioaddr + EMAC_TX_FLOW_CTL); if (fc == FLOW_AUTO) - v |= EMAC_TX_FLOW_CTL_EN; + setbits32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN); else - v &= ~EMAC_TX_FLOW_CTL_EN; - writel(v, ioaddr + EMAC_TX_FLOW_CTL); + clrbits32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN); } static int sun8i_dwmac_reset(struct stmmac_priv *priv) @@ -684,8 +654,7 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv) u32 v; int err; - v = readl(priv->ioaddr + EMAC_BASIC_CTL1); - writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); + setbits32(priv->ioaddr + EMAC_BASIC_CTL1, 0x01); /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) * need more if no cable plugged. 100ms seems OK diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c index 0877bde6e860..ca864c3d7ff3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c @@ -25,6 +25,7 @@ #include <linux/crc32.h> #include <linux/slab.h> #include <linux/ethtool.h> +#include <linux/setbits.h> #include <net/dsa.h> #include <asm/io.h> #include "stmmac.h" @@ -355,7 +356,6 @@ static void dwmac1000_set_eee_mode(struct mac_device_info *hw, bool en_tx_lpi_clockgating) { void __iomem *ioaddr = hw->pcsr; - u32 value; /*TODO - en_tx_lpi_clockgating treatment */ @@ -363,19 +363,16 @@ static void dwmac1000_set_eee_mode(struct mac_device_info *hw, * receive path and instruct the transmit to enter in LPI * state. */ - value = readl(ioaddr + LPI_CTRL_STATUS); - value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA; - writel(value, ioaddr + LPI_CTRL_STATUS); + setbits32(ioaddr + LPI_CTRL_STATUS, + LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA); } static void dwmac1000_reset_eee_mode(struct mac_device_info *hw) { void __iomem *ioaddr = hw->pcsr; - u32 value; - value = readl(ioaddr + LPI_CTRL_STATUS); - value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA); - writel(value, ioaddr + LPI_CTRL_STATUS); + clrbits32(ioaddr + LPI_CTRL_STATUS, + (LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA)); } static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link) @@ -383,14 +380,10 @@ static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link) void __iomem *ioaddr = hw->pcsr; u32 value; - value = readl(ioaddr + LPI_CTRL_STATUS); - if (link) - value |= LPI_CTRL_STATUS_PLS; + setbits32(ioaddr + LPI_CTRL_STATUS, LPI_CTRL_STATUS_PLS); else - value &= ~LPI_CTRL_STATUS_PLS; - - writel(value, ioaddr + LPI_CTRL_STATUS); + clrbits32(ioaddr + LPI_CTRL_STATUS, LPI_CTRL_STATUS_PLS); } static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index 7e5d5db0d516..998695cbf3c2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -17,6 +17,8 @@ #include <linux/slab.h> #include <linux/ethtool.h> #include <linux/io.h> +#include <linux/setbits.h> +#include <linux/setbits.h> #include <net/dsa.h> #include "stmmac.h" #include "stmmac_pcs.h" @@ -85,16 +87,11 @@ static void dwmac4_rx_queue_priority(struct mac_device_info *hw, { void __iomem *ioaddr = hw->pcsr; u32 base_register; - u32 value; base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3; - value = readl(ioaddr + base_register); - - value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue); - value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & - GMAC_RXQCTRL_PSRQX_MASK(queue); - writel(value, ioaddr + base_register); + clrsetbits32(ioaddr + base_register, GMAC_RXQCTRL_PSRQX_MASK(queue), + (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & GMAC_RXQCTRL_PSRQX_MASK(queue)); } static void dwmac4_tx_queue_priority(struct mac_device_info *hw, @@ -102,17 +99,11 @@ static void dwmac4_tx_queue_priority(struct mac_device_info *hw, { void __iomem *ioaddr = hw->pcsr; u32 base_register; - u32 value; base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1; - value = readl(ioaddr + base_register); - - value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue); - value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) & - GMAC_TXQCTRL_PSTQX_MASK(queue); - - writel(value, ioaddr + base_register); + clrsetbits32(ioaddr + base_register, GMAC_TXQCTRL_PSTQX_MASK(queue), + (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) & GMAC_TXQCTRL_PSTQX_MASK(queue)); } static void dwmac4_rx_queue_routing(struct mac_device_info *hw, @@ -198,11 +189,9 @@ static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw, u32 weight, u32 queue) { void __iomem *ioaddr = hw->pcsr; - u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); - - value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK; - value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK; - writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); + clrsetbits32(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue), + MTL_TXQ_WEIGHT_ISCQW_MASK, + weight & MTL_TXQ_WEIGHT_ISCQW_MASK); } static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan) @@ -243,10 +232,8 @@ static void dwmac4_config_cbs(struct mac_device_info *hw, pr_debug("\tlow_credit: 0x%08x\n", low_credit); /* enable AV algorithm */ - value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue)); - value |= MTL_ETS_CTRL_AVALG; - value |= MTL_ETS_CTRL_CC; - writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue)); + setbits32(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue), + MTL_ETS_CTRL_AVALG | MTL_ETS_CTRL_CC); /* configure send slope */ value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue)); @@ -360,11 +347,9 @@ static void dwmac4_set_eee_mode(struct mac_device_info *hw, static void dwmac4_reset_eee_mode(struct mac_device_info *hw) { void __iomem *ioaddr = hw->pcsr; - u32 value; - value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); - value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA); - writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); + clrbits32(ioaddr + GMAC4_LPI_CTRL_STATUS, + (GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA)); } static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link) @@ -372,14 +357,12 @@ static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link) void __iomem *ioaddr = hw->pcsr; u32 value; - value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); - if (link) - value |= GMAC4_LPI_CTRL_STATUS_PLS; + setbits32(ioaddr + GMAC4_LPI_CTRL_STATUS, + GMAC4_LPI_CTRL_STATUS_PLS); else - value &= ~GMAC4_LPI_CTRL_STATUS_PLS; - - writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); + clrbits32(ioaddr + GMAC4_LPI_CTRL_STATUS, + GMAC4_LPI_CTRL_STATUS_PLS); } static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index edb6053bd980..63c582ff24a1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -14,6 +14,7 @@ */ #include <linux/io.h> +#include <linux/setbits.h> #include "dwmac4.h" #include "dwmac4_dma.h" @@ -270,9 +271,7 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); /* Enable MTL RX overflow */ - mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); - writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, - ioaddr + MTL_CHAN_INT_CTRL(channel)); + setbits32(ioaddr + MTL_CHAN_INT_CTRL(channel), MTL_RX_OVERFLOW_INT_EN); } static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, @@ -422,12 +421,8 @@ static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) { - u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); - - value &= ~DMA_RBSZ_MASK; - value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; - - writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); + clrsetbits32(ioaddr + DMA_CHAN_RX_CONTROL(chan), DMA_RBSZ_MASK, + (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK); } const struct stmmac_dma_ops dwmac4_dma_ops = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c index 49f5687879df..5f699cf54e17 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -10,6 +10,7 @@ #include <linux/io.h> #include <linux/delay.h> +#include <linux/setbits.h> #include "common.h" #include "dwmac4_dma.h" #include "dwmac4.h" @@ -47,51 +48,26 @@ void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); - - value |= DMA_CONTROL_ST; - writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); - - value = readl(ioaddr + GMAC_CONFIG); - value |= GMAC_CONFIG_TE; - writel(value, ioaddr + GMAC_CONFIG); + setbits32(ioaddr + DMA_CHAN_TX_CONTROL(chan), DMA_CONTROL_ST); + setbits32(ioaddr + GMAC_CONFIG, GMAC_CONFIG_TE); } void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); - - value &= ~DMA_CONTROL_ST; - writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); - - value = readl(ioaddr + GMAC_CONFIG); - value &= ~GMAC_CONFIG_TE; - writel(value, ioaddr + GMAC_CONFIG); + clrbits32(ioaddr + DMA_CHAN_TX_CONTROL(chan), DMA_CONTROL_ST); + clrbits32(ioaddr + GMAC_CONFIG, GMAC_CONFIG_TE); } void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); - - value |= DMA_CONTROL_SR; - - writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); - - value = readl(ioaddr + GMAC_CONFIG); - value |= GMAC_CONFIG_RE; - writel(value, ioaddr + GMAC_CONFIG); + setbits32(ioaddr + DMA_CHAN_RX_CONTROL(chan), DMA_CONTROL_SR); + setbits32(ioaddr + GMAC_CONFIG, GMAC_CONFIG_RE); } void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); - - value &= ~DMA_CONTROL_SR; - writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); - - value = readl(ioaddr + GMAC_CONFIG); - value &= ~GMAC_CONFIG_RE; - writel(value, ioaddr + GMAC_CONFIG); + clrbits32(ioaddr + DMA_CHAN_RX_CONTROL(chan), DMA_CONTROL_SR); + clrbits32(ioaddr + GMAC_CONFIG, GMAC_CONFIG_RE); } void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c index 3f4f3132e16b..aec2fb884477 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c @@ -4,6 +4,7 @@ #include <linux/bitops.h> #include <linux/iopoll.h> +#include <linux/setbits.h> #include "common.h" #include "dwmac4.h" #include "dwmac5.h" @@ -307,9 +308,7 @@ static int dwmac5_rxp_disable(void __iomem *ioaddr) u32 val; int ret; - val = readl(ioaddr + MTL_OPERATION_MODE); - val &= ~MTL_FRPE; - writel(val, ioaddr + MTL_OPERATION_MODE); + clrbits32(ioaddr + MTL_OPERATION_MODE, MTL_FRPE); ret = readl_poll_timeout(ioaddr + MTL_RXP_CONTROL_STATUS, val, val & RXPI, 1, 10000); @@ -320,11 +319,7 @@ static int dwmac5_rxp_disable(void __iomem *ioaddr) static void dwmac5_rxp_enable(void __iomem *ioaddr) { - u32 val; - - val = readl(ioaddr + MTL_OPERATION_MODE); - val |= MTL_FRPE; - writel(val, ioaddr + MTL_OPERATION_MODE); + setbits32(ioaddr + MTL_OPERATION_MODE, MTL_FRPE); } static int dwmac5_rxp_update_single_entry(void __iomem *ioaddr, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c index 7516ca210855..acecb9f0ee4b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/iopoll.h> +#include <linux/setbits.h> #include "common.h" #include "dwmac_dma.h" @@ -59,30 +60,22 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); - value |= DMA_CONTROL_ST; - writel(value, ioaddr + DMA_CONTROL); + setbits32(ioaddr + DMA_CONTROL, DMA_CONTROL_ST); } void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); - value &= ~DMA_CONTROL_ST; - writel(value, ioaddr + DMA_CONTROL); + clrbits32(ioaddr + DMA_CONTROL, DMA_CONTROL_ST); } void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); - value |= DMA_CONTROL_SR; - writel(value, ioaddr + DMA_CONTROL); + setbits32(ioaddr + DMA_CONTROL, DMA_CONTROL_SR); } void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); - value &= ~DMA_CONTROL_SR; - writel(value, ioaddr + DMA_CONTROL); + clrbits32(ioaddr + DMA_CONTROL, DMA_CONTROL_SR); } #ifdef DWMAC_DMA_DEBUG diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 64b8cb88ea45..fc7df8de2ba7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -4,6 +4,7 @@ * stmmac XGMAC support. */ +#include <linux/setbits.h> #include "stmmac.h" #include "dwxgmac2.h" @@ -75,12 +76,10 @@ static int dwxgmac2_rx_ipc(struct mac_device_info *hw) void __iomem *ioaddr = hw->pcsr; u32 value; - value = readl(ioaddr + XGMAC_RX_CONFIG); if (hw->rx_csum) - value |= XGMAC_CONFIG_IPC; + setbits32(ioaddr + XGMAC_RX_CONFIG, XGMAC_CONFIG_IPC); else - value &= ~XGMAC_CONFIG_IPC; - writel(value, ioaddr + XGMAC_RX_CONFIG); + clrbits32(ioaddr + XGMAC_RX_CONFIG, XGMAC_CONFIG_IPC); return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC); } @@ -107,11 +106,8 @@ static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio, reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3; - value = readl(ioaddr + reg); - value &= ~XGMAC_PSRQ(queue); - value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue); - - writel(value, ioaddr + reg); + clrsetbits32(ioaddr + reg, XGMAC_PSRQ(queue), + (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue)); } static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw, @@ -170,11 +166,8 @@ static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue, reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1; - value = readl(ioaddr + reg); - value &= ~XGMAC_QxMDMACH(queue); - value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue); - - writel(value, ioaddr + reg); + clrsetbits32(ioaddr + reg, XGMAC_QxMDMACH(queue), + (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue)); } static void dwxgmac2_config_cbs(struct mac_device_info *hw, @@ -189,9 +182,8 @@ static void dwxgmac2_config_cbs(struct mac_device_info *hw, writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue)); writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue)); - value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue)); - value |= XGMAC_CC | XGMAC_CBS; - writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue)); + setbits32(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue), + XGMAC_CC | XGMAC_CBS); } static int dwxgmac2_host_irq_status(struct mac_device_info *hw, @@ -263,9 +255,7 @@ static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode) if (mode & WAKE_UCAST) val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN; if (val) { - u32 cfg = readl(ioaddr + XGMAC_RX_CONFIG); - cfg |= XGMAC_CONFIG_RE; - writel(cfg, ioaddr + XGMAC_RX_CONFIG); + setbits32(ioaddr + XGMAC_RX_CONFIG, XGMAC_CONFIG_RE); } writel(val, ioaddr + XGMAC_PMT); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 6c5092e7771c..7a7d584211e9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -5,6 +5,7 @@ */ #include <linux/iopoll.h> +#include <linux/setbits.h> #include "stmmac.h" #include "dwxgmac2.h" @@ -47,12 +48,9 @@ static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, u32 dma_rx_phy, u32 chan) { u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; - u32 value; - value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - value &= ~XGMAC_RxPBL; - value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + clrsetbits32(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan), XGMAC_RxPBL, + (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL); writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); } @@ -150,8 +148,7 @@ static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); /* Enable MTL RX overflow */ - value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); - writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); + setbits32(ioaddr + XGMAC_MTL_QINTEN(channel), XGMAC_RXOIE); } static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode, @@ -209,54 +206,26 @@ static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan) static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan) { - u32 value; - - value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - value |= XGMAC_TXST; - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - - value = readl(ioaddr + XGMAC_TX_CONFIG); - value |= XGMAC_CONFIG_TE; - writel(value, ioaddr + XGMAC_TX_CONFIG); + setbits32(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan), XGMAC_TXST); + setbits32(ioaddr + XGMAC_TX_CONFIG, XGMAC_CONFIG_TE); } static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan) { - u32 value; - - value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - value &= ~XGMAC_TXST; - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - - value = readl(ioaddr + XGMAC_TX_CONFIG); - value &= ~XGMAC_CONFIG_TE; - writel(value, ioaddr + XGMAC_TX_CONFIG); + clrbits32(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan), XGMAC_TXST); + clrbits32(ioaddr + XGMAC_TX_CONFIG, XGMAC_CONFIG_TE); } static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan) { - u32 value; - - value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - value |= XGMAC_RXST; - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - - value = readl(ioaddr + XGMAC_RX_CONFIG); - value |= XGMAC_CONFIG_RE; - writel(value, ioaddr + XGMAC_RX_CONFIG); + setbits32(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan), XGMAC_RXST); + setbits32(ioaddr + XGMAC_RX_CONFIG, XGMAC_CONFIG_RE); } static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan) { - u32 value; - - value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - value &= ~XGMAC_RXST; - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - - value = readl(ioaddr + XGMAC_RX_CONFIG); - value &= ~XGMAC_CONFIG_RE; - writel(value, ioaddr + XGMAC_RX_CONFIG); + clrbits32(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan), XGMAC_RXST); + clrbits32(ioaddr + XGMAC_RX_CONFIG, XGMAC_CONFIG_RE); } static int dwxgmac2_dma_interrupt(void __iomem *ioaddr, @@ -367,14 +336,10 @@ static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan) { - u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); - if (en) - value |= XGMAC_TSE; + setbits32(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan), XGMAC_TSE); else - value &= ~XGMAC_TSE; - - writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); + clrbits32(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan), XGMAC_TSE); } static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) @@ -394,11 +359,7 @@ static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) { - u32 value; - - value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); - value |= bfsize << 1; - writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); + setbits32(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan), bfsize << 1); } const struct stmmac_dma_ops dwxgmac210_dma_ops = { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c index 8d9cc2157afd..8680fb4b1fa8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c @@ -21,6 +21,7 @@ #include <linux/io.h> #include <linux/delay.h> +#include <linux/setbits.h> #include "common.h" #include "stmmac_ptp.h" @@ -64,14 +65,11 @@ static void config_sub_second_increment(void __iomem *ioaddr, static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec) { int limit; - u32 value; writel(sec, ioaddr + PTP_STSUR); writel(nsec, ioaddr + PTP_STNSUR); /* issue command to initialize the system time value */ - value = readl(ioaddr + PTP_TCR); - value |= PTP_TCR_TSINIT; - writel(value, ioaddr + PTP_TCR); + setbits32(ioaddr + PTP_TCR, PTP_TCR_TSINIT); /* wait for present system time initialize to complete */ limit = 10; @@ -88,14 +86,11 @@ static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec) static int config_addend(void __iomem *ioaddr, u32 addend) { - u32 value; int limit; writel(addend, ioaddr + PTP_TAR); /* issue command to update the addend value */ - value = readl(ioaddr + PTP_TCR); - value |= PTP_TCR_TSADDREG; - writel(value, ioaddr + PTP_TCR); + setbits32(ioaddr + PTP_TCR, PTP_TCR_TSADDREG); /* wait for present addend update to complete */ limit = 10; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index b72ef171477e..b9cdf951eda6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -27,6 +27,7 @@ #include <linux/of_gpio.h> #include <linux/of_mdio.h> #include <linux/phy.h> +#include <linux/setbits.h> #include <linux/slab.h> #include "dwxgmac2.h" @@ -64,10 +65,8 @@ static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, return -EBUSY; /* Set port as Clause 22 */ - tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); - tmp &= ~MII_XGMAC_C22P_MASK; - tmp |= BIT(phyaddr); - writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); + clrsetbits32(priv->ioaddr + XGMAC_MDIO_C22P, MII_XGMAC_C22P_MASK, + BIT(phyaddr)); *hw_addr = (phyaddr << 16) | (phyreg & 0x1f); return 0; -- 2.16.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe ` (3 preceding siblings ...) 2018-09-07 19:41 ` [PATCH 4/5] net: ethernet: stmmac: use xxxsetbits32 Corentin Labbe @ 2018-09-07 19:41 ` Corentin Labbe 2018-09-07 21:57 ` [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions David Miller 2018-09-10 5:24 ` Christophe LEROY 6 siblings, 0 replies; 15+ messages in thread From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw) To: linux-arm-kernel This patch converts ahci_sunxi to use xxxsetbits32 functions Signed-off-by: Corentin Labbe <clabbe@baylibre.com> --- drivers/ata/ahci_sunxi.c | 51 ++++++++++++------------------------------------ 1 file changed, 12 insertions(+), 39 deletions(-) diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index 911710643305..0799441f1237 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -25,6 +25,7 @@ #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> +#include <linux/setbits.h> #include "ahci.h" #define DRV_NAME "ahci-sunxi" @@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp, #define AHCI_P0PHYCR 0x0178 #define AHCI_P0PHYSR 0x017c -static void sunxi_clrbits(void __iomem *reg, u32 clr_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val &= ~(clr_val); - writel(reg_val, reg); -} - -static void sunxi_setbits(void __iomem *reg, u32 set_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val |= set_val; - writel(reg_val, reg); -} - -static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val &= ~(clr_val); - reg_val |= set_val; - writel(reg_val, reg); -} - static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) { return (readl(reg) >> shift) & mask; @@ -100,22 +73,22 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) writel(0, reg_base + AHCI_RWCR); msleep(5); - sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, + setbits32(reg_base + AHCI_PHYCS1R, BIT(19)); + clrsetbits32(reg_base + AHCI_PHYCS0R, (0x7 << 24), (0x5 << 24) | BIT(23) | BIT(18)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, + clrsetbits32(reg_base + AHCI_PHYCS1R, (0x3 << 16) | (0x1f << 8) | (0x3 << 6), (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); - sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); - sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, + setbits32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); + clrbits32(reg_base + AHCI_PHYCS1R, BIT(19)); + clrsetbits32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, + clrsetbits32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); msleep(5); - sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + setbits32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); timeout = 250; /* Power up takes aprox 50 us */ do { @@ -130,7 +103,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) udelay(1); } while (1); - sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + setbits32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); timeout = 100; /* Calibration takes aprox 10 us */ do { @@ -158,10 +131,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap) struct ahci_host_priv *hpriv = ap->host->private_data; /* Setup DMA before DMA start */ - sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); + clrsetbits32(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); /* Start DMA */ - sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); + setbits32(port_mmio + PORT_CMD, PORT_CMD_START); } static const struct ata_port_info ahci_sunxi_port_info = { -- 2.16.4 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe ` (4 preceding siblings ...) 2018-09-07 19:41 ` [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions Corentin Labbe @ 2018-09-07 21:57 ` David Miller 2018-09-10 5:24 ` Christophe LEROY 6 siblings, 0 replies; 15+ messages in thread From: David Miller @ 2018-09-07 21:57 UTC (permalink / raw) To: linux-arm-kernel If you are going to do this, please add for_each_set_bit64() and similar. For example, see: https://marc.info/?l=linux-netdev&m=153633391214025&w=2 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe ` (5 preceding siblings ...) 2018-09-07 21:57 ` [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions David Miller @ 2018-09-10 5:24 ` Christophe LEROY 6 siblings, 0 replies; 15+ messages in thread From: Christophe LEROY @ 2018-09-10 5:24 UTC (permalink / raw) To: linux-arm-kernel Le 07/09/2018 ? 21:41, Corentin Labbe a ?crit?: > Hello > > This patchset adds a new set of functions which are open-coded in lot of > place. > Basicly the pattern is always the same, "read, modify a bit, write" > some driver already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b) > > The first patch rename some powerpc funtions which already use the same name (xxxbits32) > but with only bigendian values. The same name as what ? > > The second patch adds the header. But the second patch adds functions with the same name as the powerpc ones but doing something different. Why consider that setbits32() should be LE and not BE ? Christophe > The third patch is an ugly try to implement a coccinelle semantic patch to > find all place where xxxbits function could be used. > Probably this spatch could be better written and I didnt found an easy way to add the "linux/setbits" header. > > The two last patch are example of convertion of two drivers. > Thoses patchs give an example of the reduction of code won by using xxxbits32. > > This patchset is tested with the ahci_sunxi and dwmac-sun8i drivers. > > Regards > > Corentin Labbe (5): > powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be > include: add > setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in > linux/setbits.h > coccinelle: add xxxsetbitsXX converting spatch > net: ethernet: stmmac: use xxxsetbits32 > ata: ahci_sunxi: use xxxsetbits32 functions > > arch/powerpc/include/asm/fsl_lbc.h | 2 +- > arch/powerpc/include/asm/io.h | 5 +- > arch/powerpc/platforms/44x/canyonlands.c | 4 +- > arch/powerpc/platforms/4xx/gpio.c | 28 +- > arch/powerpc/platforms/512x/pdm360ng.c | 6 +- > arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +- > arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 +- > arch/powerpc/platforms/82xx/ep8248e.c | 2 +- > arch/powerpc/platforms/82xx/km82xx.c | 6 +- > arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +- > arch/powerpc/platforms/82xx/pq2.c | 2 +- > arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +- > arch/powerpc/platforms/82xx/pq2fads.c | 10 +- > arch/powerpc/platforms/83xx/km83xx.c | 6 +- > arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- > arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +- > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +- > arch/powerpc/platforms/85xx/p1022_ds.c | 4 +- > arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +- > arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +- > arch/powerpc/platforms/85xx/twr_p102x.c | 2 +- > arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +- > arch/powerpc/platforms/8xx/adder875.c | 2 +- > arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +- > arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +- > arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +- > arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +- > arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +- > arch/powerpc/platforms/embedded6xx/wii.c | 10 +- > arch/powerpc/sysdev/cpm1.c | 26 +- > arch/powerpc/sysdev/cpm2.c | 16 +- > arch/powerpc/sysdev/cpm_common.c | 4 +- > arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +- > arch/powerpc/sysdev/fsl_lbc.c | 2 +- > arch/powerpc/sysdev/fsl_pci.c | 8 +- > arch/powerpc/sysdev/fsl_pmc.c | 2 +- > arch/powerpc/sysdev/fsl_rcpm.c | 74 ++-- > arch/powerpc/sysdev/fsl_rio.c | 4 +- > arch/powerpc/sysdev/fsl_rmu.c | 8 +- > arch/powerpc/sysdev/mpic_timer.c | 12 +- > drivers/ata/ahci_sunxi.c | 51 +-- > .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 54 +-- > drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 55 +-- > .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 21 +- > drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 51 +-- > drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 13 +- > drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 42 +- > drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 11 +- > drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 17 +- > .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 30 +- > drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 69 +--- > .../net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 11 +- > drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 7 +- > include/linux/setbits.h | 55 +++ > scripts/coccinelle/misc/setbits.cocci | 423 +++++++++++++++++++++ > 56 files changed, 776 insertions(+), 489 deletions(-) > create mode 100644 include/linux/setbits.h > create mode 100644 scripts/coccinelle/misc/setbits.cocci > ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-09-10 18:53 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-09-07 19:41 [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions Corentin Labbe 2018-09-07 19:41 ` [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be Corentin Labbe 2018-09-10 5:16 ` Christophe LEROY 2018-09-10 18:50 ` LABBE Corentin 2018-09-07 19:41 ` [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h Corentin Labbe 2018-09-07 20:00 ` Scott Wood 2018-09-10 18:49 ` LABBE Corentin 2018-09-10 5:22 ` Christophe LEROY 2018-09-10 18:53 ` LABBE Corentin 2018-09-07 19:41 ` [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch Corentin Labbe 2018-09-09 11:13 ` SF Markus Elfring 2018-09-07 19:41 ` [PATCH 4/5] net: ethernet: stmmac: use xxxsetbits32 Corentin Labbe 2018-09-07 19:41 ` [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions Corentin Labbe 2018-09-07 21:57 ` [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions David Miller 2018-09-10 5:24 ` Christophe LEROY
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