* [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC
@ 2018-09-24 0:08 Vabhav Sharma
2018-09-24 0:08 ` [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Vabhav Sharma @ 2018-09-24 0:08 UTC (permalink / raw)
To: linux-arm-kernel
Changes for v3:
-Split clockgen support patch into below two patches:
- a)Updated array size of cmux_to_group[] with NUM_CMUX+1 to include -1
terminator and p4080 cmux_to_group[] array with -1 terminator
- b)Add clockgen support for lx2160a
Changes for v2:
- Modified cmux_to_group array to include -1 terminator
- Revert NUM_CMUX to original value 8 from 16
- Remove ?As LX2160A is 16 core, so modified value for NUM_CMUX?
in patch "[PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
lx2160a" description
- Populated cache properties for L1 and L2 cache in lx2160a device-tree.
- Removed reboot node from lx2160a device-tree as PSCI is implemented.
- Removed incorrect comment for timer node interrupt property in
lx2160a device-tree.
- Modified pmu node compatible property from "arm,armv8-pmuv3" to
"arm,cortex-a72-pmu" in lx2160a device-tree
- Non-standard aliases removed in lx2160a rdb board device-tree
- Updated i2c child nodes to generic name in lx2160a rdb device-tree.
Changes for v1:
- Add compatible string for LX2160A clockgen support
- Add compatible string to initialize LX2160A guts driver
- Add compatible string for LX2160A support in dt-bindings
- Add dts file to enable support for LX2160A SoC and LX2160A RDB
(Reference design board)
Vabhav Sharma (4):
dt-bindings: arm64: add compatible for LX2160A
soc/fsl/guts: Add compatible string for LX2160A
arm64: dts: add QorIQ LX2160A SoC support
arm64: dts: add LX2160ARDB board support
Yogesh Gaur (2):
drivers: clk-qoriq: increase array size of cmux_to_group
drivers: clk-qoriq: Add clockgen support for lx2160a
Documentation/devicetree/bindings/arm/fsl.txt | 12 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 88 +++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 693 ++++++++++++++++++++++
drivers/clk/clk-qoriq.c | 16 +-
drivers/cpufreq/qoriq-cpufreq.c | 1 +
drivers/soc/fsl/guts.c | 1 +
7 files changed, 810 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
--
2.7.4
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma @ 2018-09-24 0:08 ` Vabhav Sharma 2018-09-27 19:32 ` Rob Herring 2018-09-24 0:08 ` [PATCH v3 2/6] soc/fsl/guts: Add compatible string " Vabhav Sharma ` (4 subsequent siblings) 5 siblings, 1 reply; 16+ messages in thread From: Vabhav Sharma @ 2018-09-24 0:08 UTC (permalink / raw) To: linux-arm-kernel Add compatible for LX2160A SoC,QDS and RDB board Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> --- Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index cdb9dd7..76256bd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -218,3 +218,15 @@ Required root node properties: LS2088A ARMv8 based RDB Board Required root node properties: - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; + +LX2160A SoC +Required root node properties: + - compatible = "fsl,lx2160a"; + +LX2160A ARMv8 based QDS Board +Required root node properties: + - compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; + +LX2160A ARMv8 based RDB Board +Required root node properties: + - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A 2018-09-24 0:08 ` [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma @ 2018-09-27 19:32 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2018-09-27 19:32 UTC (permalink / raw) To: linux-arm-kernel On Mon, 24 Sep 2018 05:38:56 +0530, Vabhav Sharma wrote: > Add compatible for LX2160A SoC,QDS and RDB board > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> > --- > Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/6] soc/fsl/guts: Add compatible string for LX2160A 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma @ 2018-09-24 0:08 ` Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group Vabhav Sharma ` (3 subsequent siblings) 5 siblings, 0 replies; 16+ messages in thread From: Vabhav Sharma @ 2018-09-24 0:08 UTC (permalink / raw) To: linux-arm-kernel Adding compatible string "lx2160a-dcfg" to initialize guts driver for lx2160 Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> --- drivers/soc/fsl/guts.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c index 302e0c8..5e1e633 100644 --- a/drivers/soc/fsl/guts.c +++ b/drivers/soc/fsl/guts.c @@ -222,6 +222,7 @@ static const struct of_device_id fsl_guts_of_match[] = { { .compatible = "fsl,ls1088a-dcfg", }, { .compatible = "fsl,ls1012a-dcfg", }, { .compatible = "fsl,ls1046a-dcfg", }, + { .compatible = "fsl,lx2160a-dcfg", }, {} }; MODULE_DEVICE_TABLE(of, fsl_guts_of_match); -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 2/6] soc/fsl/guts: Add compatible string " Vabhav Sharma @ 2018-09-24 0:08 ` Vabhav Sharma 2018-10-01 22:04 ` Stephen Boyd 2018-09-24 0:08 ` [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma ` (2 subsequent siblings) 5 siblings, 1 reply; 16+ messages in thread From: Vabhav Sharma @ 2018-09-24 0:08 UTC (permalink / raw) To: linux-arm-kernel From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Increase size of cmux_to_group array, to accomdate entry of -1 termination. Added -1, terminated, entry for 4080_cmux_grpX. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> --- drivers/clk/clk-qoriq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 3a1812f..e152bfb 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -79,7 +79,7 @@ struct clockgen_chipinfo { const struct clockgen_muxinfo *cmux_groups[2]; const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL]; void (*init_periph)(struct clockgen *cg); - int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */ + int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */ u32 pll_mask; /* 1 << n bit set if PLL n is valid */ u32 flags; /* CG_xxx */ }; @@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = { &p4080_cmux_grp1, &p4080_cmux_grp2 }, .cmux_to_group = { - 0, 0, 0, 0, 1, 1, 1, 1 + 0, 0, 0, 0, 1, 1, 1, 1, -1 }, .pll_mask = 0x1f, }, -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group 2018-09-24 0:08 ` [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group Vabhav Sharma @ 2018-10-01 22:04 ` Stephen Boyd 2018-10-03 14:25 ` Vabhav Sharma 0 siblings, 1 reply; 16+ messages in thread From: Stephen Boyd @ 2018-10-01 22:04 UTC (permalink / raw) To: linux-arm-kernel Subject should be "clk: qoriq: increase array size ..." ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group 2018-10-01 22:04 ` Stephen Boyd @ 2018-10-03 14:25 ` Vabhav Sharma 0 siblings, 0 replies; 16+ messages in thread From: Vabhav Sharma @ 2018-10-03 14:25 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: Tuesday, October 2, 2018 3:34 AM > To: Vabhav Sharma <vabhav.sharma@nxp.com>; arnd at arndb.de; > catalin.marinas at arm.com; devicetree at vger.kernel.org; > gregkh at linuxfoundation.org; kstewart at linuxfoundation.org; linux-arm- > kernel at lists.infradead.org; linux-clk at vger.kernel.org; linux-kernel- > owner at vger.kernel.org; linux-kernel at vger.kernel.org; linux- > pm at vger.kernel.org; linuxppc-dev at lists.ozlabs.org; mark.rutland at arm.com; > mturquette at baylibre.com; oss at buserror.net; rjw at rjwysocki.net; > robh+dt at kernel.org; sudeep.holla at arm.com; viresh.kumar at linaro.org; > will.deacon at arm.com; yamada.masahiro at socionext.com > Cc: linux at armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>; Udit Kumar > <udit.kumar@nxp.com>; Yogesh Narayan Gaur > <yogeshnarayan.gaur@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com> > Subject: Re: [PATCH v3 3/6] drivers: clk-qoriq: increase array size of > cmux_to_group > > Subject should be "clk: qoriq: increase array size ..." Ok ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma ` (2 preceding siblings ...) 2018-09-24 0:08 ` [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group Vabhav Sharma @ 2018-09-24 0:08 ` Vabhav Sharma 2018-10-01 22:04 ` Stephen Boyd 2018-09-24 0:09 ` [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma 2018-09-24 0:09 ` [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support Vabhav Sharma 5 siblings, 1 reply; 16+ messages in thread From: Vabhav Sharma @ 2018-09-24 0:08 UTC (permalink / raw) To: linux-arm-kernel From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Add clockgen support for lx2160a. Added entry for compat 'fsl,lx2160a-clockgen'. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/clk-qoriq.c | 12 ++++++++++++ drivers/cpufreq/qoriq-cpufreq.c | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index e152bfb..99675de 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = { .flags = CG_VER3 | CG_LITTLE_ENDIAN, }, { + .compat = "fsl,lx2160a-clockgen", + .cmux_groups = { + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb + }, + .cmux_to_group = { + 0, 0, 0, 0, 1, 1, 1, 1, -1 + }, + .pll_mask = 0x37, + .flags = CG_VER3 | CG_LITTLE_ENDIAN, + }, + { .compat = "fsl,p2041-clockgen", .guts_compat = "fsl,qoriq-device-config-1.0", .init_periph = p2041_init_periph, @@ -1424,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); +CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init); /* Legacy nodes */ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c index 3d773f6..83921b7 100644 --- a/drivers/cpufreq/qoriq-cpufreq.c +++ b/drivers/cpufreq/qoriq-cpufreq.c @@ -295,6 +295,7 @@ static const struct of_device_id node_matches[] __initconst = { { .compatible = "fsl,ls1046a-clockgen", }, { .compatible = "fsl,ls1088a-clockgen", }, { .compatible = "fsl,ls2080a-clockgen", }, + { .compatible = "fsl,lx2160a-clockgen", }, { .compatible = "fsl,p4080-clockgen", }, { .compatible = "fsl,qoriq-clockgen-1.0", }, { .compatible = "fsl,qoriq-clockgen-2.0", }, -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a 2018-09-24 0:08 ` [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma @ 2018-10-01 22:04 ` Stephen Boyd 2018-10-03 14:25 ` Vabhav Sharma 0 siblings, 1 reply; 16+ messages in thread From: Stephen Boyd @ 2018-10-01 22:04 UTC (permalink / raw) To: linux-arm-kernel Same subject comment. Quoting Vabhav Sharma (2018-09-23 17:08:59) > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > > Add clockgen support for lx2160a. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a 2018-10-01 22:04 ` Stephen Boyd @ 2018-10-03 14:25 ` Vabhav Sharma 0 siblings, 0 replies; 16+ messages in thread From: Vabhav Sharma @ 2018-10-03 14:25 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: devicetree-owner at vger.kernel.org <devicetree-owner@vger.kernel.org> > On Behalf Of Stephen Boyd > Sent: Tuesday, October 2, 2018 3:34 AM > To: Vabhav Sharma <vabhav.sharma@nxp.com>; arnd at arndb.de; > catalin.marinas at arm.com; devicetree at vger.kernel.org; > gregkh at linuxfoundation.org; kstewart at linuxfoundation.org; linux-arm- > kernel at lists.infradead.org; linux-clk at vger.kernel.org; linux-kernel- > owner at vger.kernel.org; linux-kernel at vger.kernel.org; linux- > pm at vger.kernel.org; linuxppc-dev at lists.ozlabs.org; mark.rutland at arm.com; > mturquette at baylibre.com; oss at buserror.net; rjw at rjwysocki.net; > robh+dt at kernel.org; sudeep.holla at arm.com; viresh.kumar at linaro.org; > will.deacon at arm.com; yamada.masahiro at socionext.com > Cc: linux at armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>; Udit Kumar > <udit.kumar@nxp.com>; Yogesh Narayan Gaur > <yogeshnarayan.gaur@nxp.com>; Andy Tang <andy.tang@nxp.com>; Vabhav > Sharma <vabhav.sharma@nxp.com> > Subject: Re: [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a > > Same subject comment. Ok > > Quoting Vabhav Sharma (2018-09-23 17:08:59) > > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > > > > Add clockgen support for lx2160a. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma ` (3 preceding siblings ...) 2018-09-24 0:08 ` [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma @ 2018-09-24 0:09 ` Vabhav Sharma 2018-09-28 20:41 ` Li Yang 2018-09-24 0:09 ` [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support Vabhav Sharma 5 siblings, 1 reply; 16+ messages in thread From: Vabhav Sharma @ 2018-09-24 0:09 UTC (permalink / raw) To: linux-arm-kernel LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA UARTs etc. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 693 +++++++++++++++++++++++++ 1 file changed, 693 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi new file mode 100644 index 0000000..46eea16 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -0,0 +1,693 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree Include file for Layerscape-LX2160A family SoC. +// +// Copyright 2018 NXP + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + // 8 clusters having 2 Cortex-A72 cores each + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + clocks = <&clockgen 1 0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster0_l2>; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + clocks = <&clockgen 1 0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster0_l2>; + }; + + cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x100>; + clocks = <&clockgen 1 1>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster1_l2>; + }; + + cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x101>; + clocks = <&clockgen 1 1>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster1_l2>; + }; + + cpu at 200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x200>; + clocks = <&clockgen 1 2>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster2_l2>; + }; + + cpu at 201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x201>; + clocks = <&clockgen 1 2>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster2_l2>; + }; + + cpu at 300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x300>; + clocks = <&clockgen 1 3>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster3_l2>; + }; + + cpu at 301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x301>; + clocks = <&clockgen 1 3>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster3_l2>; + }; + + cpu at 400 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x400>; + clocks = <&clockgen 1 4>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster4_l2>; + }; + + cpu at 401 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x401>; + clocks = <&clockgen 1 4>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster4_l2>; + }; + + cpu at 500 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x500>; + clocks = <&clockgen 1 5>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster5_l2>; + }; + + cpu at 501 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x501>; + clocks = <&clockgen 1 5>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster5_l2>; + }; + + cpu at 600 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x600>; + clocks = <&clockgen 1 6>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster6_l2>; + }; + + cpu at 601 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x601>; + clocks = <&clockgen 1 6>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster6_l2>; + }; + + cpu at 700 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x700>; + clocks = <&clockgen 1 7>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster7_l2>; + }; + + cpu at 701 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x701>; + clocks = <&clockgen 1 7>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster7_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster4_l2: l2-cache4 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster5_l2: l2-cache5 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster6_l2: l2-cache6 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster7_l2: l2-cache7 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + }; + + gic: interrupt-controller at 6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + + // SGI_base) + <0x0 0x0c0c0000 0 0x2000>, // GICC + <0x0 0x0c0d0000 0 0x1000>, // GICH + <0x0 0x0c0e0000 0 0x20000>; // GICV + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + interrupts = <1 9 0x4>; + + its: gic-its at 6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + rstcr: syscon at 1e60000 { + compatible = "syscon"; + reg = <0x0 0x1e60000 0x0 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <1 7 0x8>; // PMU PPI, Level low type + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + memory at 80000000 { + // DRAM space - 1, size : 2 GB DRAM + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + ddr1: memory-controller at 1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = <0 17 0x4>; + little-endian; + }; + + ddr2: memory-controller at 1090000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1090000 0x0 0x1000>; + interrupts = <0 18 0x4>; + little-endian; + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking at 1300000 { + compatible = "fsl,lx2160a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + crypto: crypto at 8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + status = "disabled"; + + sec_jr0: jr at 10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr at 20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr at 30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr at 40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + dcfg: dcfg at 1e00000 { + compatible = "fsl,lx2160a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + gpio0: gpio at 2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 0x4>; // Level high type + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio at 2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 0x4>; // Level high type + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 0x4>; // Level high type + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 0x4>; // Level high type + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + + i2c0: i2c at 2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + fsl-scl-gpio = <&gpio2 15 0>; + status = "disabled"; + }; + + i2c1: i2c at 2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c2: i2c at 2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c3: i2c at 2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c4: i2c at 2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <0 74 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + fsl-scl-gpio = <&gpio2 16 0>; + status = "disabled"; + }; + + i2c5: i2c at 2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <0 74 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c6: i2c at 2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <0 75 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c7: i2c at 2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <0 75 0x4>; // Level high type + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + uart0: serial at 21c0000 { + device_type = "serial"; + compatible = "arm,pl011","arm,sbsa-uart"; + reg = <0x0 0x21c0000 0x0 0x1000>; + interrupts = <0 32 0x4>; // Level high type + current-speed = <115200>; + status = "disabled"; + }; + + uart1: serial at 21d0000 { + device_type = "serial"; + compatible = "arm,pl011","arm,sbsa-uart"; + reg = <0x0 0x21d0000 0x0 0x1000>; + interrupts = <0 33 0x4>; // Level high type + current-speed = <115200>; + status = "disabled"; + }; + + uart2: serial at 21e0000 { + device_type = "serial"; + compatible = "arm,pl011","arm,sbsa-uart"; + reg = <0x0 0x21e0000 0x0 0x1000>; + interrupts = <0 72 0x4>; // Level high type + current-speed = <115200>; + status = "disabled"; + }; + + uart3: serial at 21f0000 { + device_type = "serial"; + compatible = "arm,pl011","arm,sbsa-uart"; + reg = <0x0 0x21f0000 0x0 0x1000>; + interrupts = <0 73 0x4>; // Level high type + current-speed = <115200>; + status = "disabled"; + }; + + smmu: iommu at 5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + #global-interrupts = <14>; + interrupts = <0 13 4>, // global secure fault + <0 14 4>, // combined secure interrupt + <0 15 4>, // global non-secure fault + <0 16 4>, // combined non-secure interrupt + // performance counter interrupts 0-9 + <0 211 4>, <0 212 4>, + <0 213 4>, <0 214 4>, + <0 215 4>, <0 216 4>, + <0 217 4>, <0 218 4>, + <0 219 4>, <0 220 4>, + // per context interrupt, 64 interrupts + <0 146 4>, <0 147 4>, + <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, + <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, + <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, + <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, + <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, + <0 168 4>, <0 169 4>, + <0 170 4>, <0 171 4>, + <0 172 4>, <0 173 4>, + <0 174 4>, <0 175 4>, + <0 176 4>, <0 177 4>, + <0 178 4>, <0 179 4>, + <0 180 4>, <0 181 4>, + <0 182 4>, <0 183 4>, + <0 184 4>, <0 185 4>, + <0 186 4>, <0 187 4>, + <0 188 4>, <0 189 4>, + <0 190 4>, <0 191 4>, + <0 192 4>, <0 193 4>, + <0 194 4>, <0 195 4>, + <0 196 4>, <0 197 4>, + <0 198 4>, <0 199 4>, + <0 200 4>, <0 201 4>, + <0 202 4>, <0 203 4>, + <0 204 4>, <0 205 4>, + <0 206 4>, <0 207 4>, + <0 208 4>, <0 209 4>; + dma-coherent; + }; + + usb0: usb3 at 3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; // Level high type + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + usb1: usb3 at 3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; // Level high type + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + watchdog at 23a0000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x23a0000 0 0x1000>, + <0x0 0x2390000 0 0x1000>; + interrupts = <0 59 4>; + timeout-sec = <30>; + }; + + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support 2018-09-24 0:09 ` [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma @ 2018-09-28 20:41 ` Li Yang 2018-10-01 12:19 ` Vabhav Sharma 0 siblings, 1 reply; 16+ messages in thread From: Li Yang @ 2018-09-28 20:41 UTC (permalink / raw) To: linux-arm-kernel On Mon, Sep 24, 2018 at 7:47 AM Vabhav Sharma <vabhav.sharma@nxp.com> wrote: > > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. > > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores > in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C > controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA > UARTs etc. > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> > --- > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 693 +++++++++++++++++++++++++ > 1 file changed, 693 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > new file mode 100644 > index 0000000..46eea16 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > @@ -0,0 +1,693 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +// > +// Device Tree Include file for Layerscape-LX2160A family SoC. > +// > +// Copyright 2018 NXP > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> You included the header file, but you didn't use the MACROs in most of the interrupts property below. It is recommended to use them for better readibity. > + > +/memreserve/ 0x80000000 0x00010000; > + > +/ { > + compatible = "fsl,lx2160a"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + // 8 clusters having 2 Cortex-A72 cores each > + cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x0>; > + clocks = <&clockgen 1 0>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster0_l2>; enable-method is a required property for this and cpu below. > + }; > + > + cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x1>; > + clocks = <&clockgen 1 0>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster0_l2>; > + }; > + > + cpu at 100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x100>; > + clocks = <&clockgen 1 1>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster1_l2>; > + }; > + > + cpu at 101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x101>; > + clocks = <&clockgen 1 1>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster1_l2>; > + }; > + > + cpu at 200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x200>; > + clocks = <&clockgen 1 2>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster2_l2>; > + }; > + > + cpu at 201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x201>; > + clocks = <&clockgen 1 2>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster2_l2>; > + }; > + > + cpu at 300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x300>; > + clocks = <&clockgen 1 3>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster3_l2>; > + }; > + > + cpu at 301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x301>; > + clocks = <&clockgen 1 3>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster3_l2>; > + }; > + > + cpu at 400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x400>; > + clocks = <&clockgen 1 4>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster4_l2>; > + }; > + > + cpu at 401 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x401>; > + clocks = <&clockgen 1 4>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster4_l2>; > + }; > + > + cpu at 500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x500>; > + clocks = <&clockgen 1 5>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster5_l2>; > + }; > + > + cpu at 501 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x501>; > + clocks = <&clockgen 1 5>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster5_l2>; > + }; > + > + cpu at 600 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x600>; > + clocks = <&clockgen 1 6>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster6_l2>; > + }; > + > + cpu at 601 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x601>; > + clocks = <&clockgen 1 6>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster6_l2>; > + }; > + > + cpu at 700 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x700>; > + clocks = <&clockgen 1 7>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster7_l2>; > + }; > + > + cpu at 701 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x701>; > + clocks = <&clockgen 1 7>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <192>; > + next-level-cache = <&cluster7_l2>; > + }; > + > + cluster0_l2: l2-cache0 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster1_l2: l2-cache1 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster2_l2: l2-cache2 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster3_l2: l2-cache3 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster4_l2: l2-cache4 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster5_l2: l2-cache5 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster6_l2: l2-cache6 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + > + cluster7_l2: l2-cache7 { > + compatible = "cache"; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <2>; > + }; > + }; > + > + gic: interrupt-controller at 6000000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist > + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + > + // SGI_base) > + <0x0 0x0c0c0000 0 0x2000>, // GICC > + <0x0 0x0c0d0000 0 0x1000>, // GICH > + <0x0 0x0c0e0000 0 0x20000>; // GICV > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + interrupts = <1 9 0x4>; > + > + its: gic-its at 6020000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0x6020000 0 0x20000>; > + }; > + }; > + > + rstcr: syscon at 1e60000 { > + compatible = "syscon"; > + reg = <0x0 0x1e60000 0x0 0x4>; > + }; This is no use if you don't have a syscon-reboot node pointing to it. > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <1 13 4>, > + <1 14 4>, > + <1 11 4>, > + <1 10 4>; > + }; > + > + pmu { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = <1 7 0x8>; // PMU PPI, Level low type > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + memory at 80000000 { > + // DRAM space - 1, size : 2 GB DRAM > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0 0x80000000>; > + }; > + > + ddr1: memory-controller at 1080000 { > + compatible = "fsl,qoriq-memory-controller"; > + reg = <0x0 0x1080000 0x0 0x1000>; > + interrupts = <0 17 0x4>; > + little-endian; > + }; > + > + ddr2: memory-controller at 1090000 { > + compatible = "fsl,qoriq-memory-controller"; > + reg = <0x0 0x1090000 0x0 0x1000>; > + interrupts = <0 18 0x4>; > + little-endian; > + }; > + > + sysclk: sysclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "sysclk"; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clockgen: clocking at 1300000 { > + compatible = "fsl,lx2160a-clockgen"; Also update the binding to include this new compatible. > + reg = <0 0x1300000 0 0xa0000>; > + #clock-cells = <2>; > + clocks = <&sysclk>; > + }; > + > + crypto: crypto at 8000000 { > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; > + fsl,sec-era = <10>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x00 0x8000000 0x100000>; > + reg = <0x00 0x8000000 0x0 0x100000>; > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; > + dma-coherent; > + status = "disabled"; > + > + sec_jr0: jr at 10000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x10000 0x10000>; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr1: jr at 20000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x20000 0x10000>; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr2: jr at 30000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x30000 0x10000>; > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr3: jr at 40000 { > + compatible = "fsl,sec-v5.0-job-ring", > + "fsl,sec-v4.0-job-ring"; > + reg = <0x40000 0x10000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + dcfg: dcfg at 1e00000 { > + compatible = "fsl,lx2160a-dcfg", "syscon"; Update the binding to include this new compatible. > + reg = <0x0 0x1e00000 0x0 0x10000>; > + little-endian; > + }; > + > + gpio0: gpio at 2300000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2300000 0x0 0x10000>; > + interrupts = <0 36 0x4>; // Level high type > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio1: gpio at 2310000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2310000 0x0 0x10000>; > + interrupts = <0 36 0x4>; // Level high type > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio at 2320000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2320000 0x0 0x10000>; > + interrupts = <0 37 0x4>; // Level high type > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio at 2330000 { > + compatible = "fsl,qoriq-gpio"; > + reg = <0x0 0x2330000 0x0 0x10000>; > + interrupts = <0 37 0x4>; // Level high type > + gpio-controller; > + little-endian; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + One new line is enough. > + i2c0: i2c at 2000000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2000000 0x0 0x10000>; > + interrupts = <0 34 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + fsl-scl-gpio = <&gpio2 15 0>; > + status = "disabled"; > + }; > + > + i2c1: i2c at 2010000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2010000 0x0 0x10000>; > + interrupts = <0 34 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c2: i2c at 2020000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2020000 0x0 0x10000>; > + interrupts = <0 35 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c3: i2c at 2030000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2030000 0x0 0x10000>; > + interrupts = <0 35 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c4: i2c at 2040000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2040000 0x0 0x10000>; > + interrupts = <0 74 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + fsl-scl-gpio = <&gpio2 16 0>; > + status = "disabled"; > + }; > + > + i2c5: i2c at 2050000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2050000 0x0 0x10000>; > + interrupts = <0 74 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c6: i2c at 2060000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2060000 0x0 0x10000>; > + interrupts = <0 75 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + i2c7: i2c at 2070000 { > + compatible = "fsl,vf610-i2c"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0 0x2070000 0x0 0x10000>; > + interrupts = <0 75 0x4>; // Level high type > + clock-names = "i2c"; > + clocks = <&clockgen 4 7>; > + status = "disabled"; > + }; > + > + uart0: serial at 21c0000 { > + device_type = "serial"; > + compatible = "arm,pl011","arm,sbsa-uart"; >From the sbsa_uart binding: This UART uses a subset of the PL011 registers and consequently lives in the PL011 driver. It's baudrate and other communication parameters cannot be adjusted at runtime, so it lacks a clock specifier here. So it is a more specific variant of pl011. Put the sbsa-uart compatible first. > + reg = <0x0 0x21c0000 0x0 0x1000>; > + interrupts = <0 32 0x4>; // Level high type > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + uart1: serial at 21d0000 { > + device_type = "serial"; > + compatible = "arm,pl011","arm,sbsa-uart"; > + reg = <0x0 0x21d0000 0x0 0x1000>; > + interrupts = <0 33 0x4>; // Level high type > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + uart2: serial at 21e0000 { > + device_type = "serial"; > + compatible = "arm,pl011","arm,sbsa-uart"; > + reg = <0x0 0x21e0000 0x0 0x1000>; > + interrupts = <0 72 0x4>; // Level high type > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + uart3: serial at 21f0000 { > + device_type = "serial"; > + compatible = "arm,pl011","arm,sbsa-uart"; > + reg = <0x0 0x21f0000 0x0 0x1000>; > + interrupts = <0 73 0x4>; // Level high type > + current-speed = <115200>; > + status = "disabled"; > + }; > + > + smmu: iommu at 5000000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x5000000 0 0x800000>; > + #iommu-cells = <1>; > + #global-interrupts = <14>; > + interrupts = <0 13 4>, // global secure fault > + <0 14 4>, // combined secure interrupt > + <0 15 4>, // global non-secure fault > + <0 16 4>, // combined non-secure interrupt > + // performance counter interrupts 0-9 > + <0 211 4>, <0 212 4>, > + <0 213 4>, <0 214 4>, > + <0 215 4>, <0 216 4>, > + <0 217 4>, <0 218 4>, > + <0 219 4>, <0 220 4>, > + // per context interrupt, 64 interrupts > + <0 146 4>, <0 147 4>, > + <0 148 4>, <0 149 4>, > + <0 150 4>, <0 151 4>, > + <0 152 4>, <0 153 4>, > + <0 154 4>, <0 155 4>, > + <0 156 4>, <0 157 4>, > + <0 158 4>, <0 159 4>, > + <0 160 4>, <0 161 4>, > + <0 162 4>, <0 163 4>, > + <0 164 4>, <0 165 4>, > + <0 166 4>, <0 167 4>, > + <0 168 4>, <0 169 4>, > + <0 170 4>, <0 171 4>, > + <0 172 4>, <0 173 4>, > + <0 174 4>, <0 175 4>, > + <0 176 4>, <0 177 4>, > + <0 178 4>, <0 179 4>, > + <0 180 4>, <0 181 4>, > + <0 182 4>, <0 183 4>, > + <0 184 4>, <0 185 4>, > + <0 186 4>, <0 187 4>, > + <0 188 4>, <0 189 4>, > + <0 190 4>, <0 191 4>, > + <0 192 4>, <0 193 4>, > + <0 194 4>, <0 195 4>, > + <0 196 4>, <0 197 4>, > + <0 198 4>, <0 199 4>, > + <0 200 4>, <0 201 4>, > + <0 202 4>, <0 203 4>, > + <0 204 4>, <0 205 4>, > + <0 206 4>, <0 207 4>, > + <0 208 4>, <0 209 4>; > + dma-coherent; > + }; > + > + usb0: usb3 at 3100000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x3100000 0x0 0x10000>; > + interrupts = <0 80 0x4>; // Level high type > + dr_mode = "host"; > + snps,quirk-frame-length-adjustment = <0x20>; > + snps,dis_rxdet_inp3_quirk; > + status = "disabled"; > + }; > + > + usb1: usb3 at 3110000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x3110000 0x0 0x10000>; > + interrupts = <0 81 0x4>; // Level high type > + dr_mode = "host"; > + snps,quirk-frame-length-adjustment = <0x20>; > + snps,dis_rxdet_inp3_quirk; > + status = "disabled"; > + }; > + > + watchdog at 23a0000 { > + compatible = "arm,sbsa-gwdt"; > + reg = <0x0 0x23a0000 0 0x1000>, > + <0x0 0x2390000 0 0x1000>; > + interrupts = <0 59 4>; > + timeout-sec = <30>; > + }; > + No new line is needed here. > + }; > +}; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support 2018-09-28 20:41 ` Li Yang @ 2018-10-01 12:19 ` Vabhav Sharma 0 siblings, 0 replies; 16+ messages in thread From: Vabhav Sharma @ 2018-10-01 12:19 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: linux-kernel-owner at vger.kernel.org <linux-kernel- > owner at vger.kernel.org> On Behalf Of Li Yang > Sent: Saturday, September 29, 2018 2:11 AM > To: Vabhav Sharma <vabhav.sharma@nxp.com> > Cc: Sudeep Holla <sudeep.holla@arm.com>; Scott Wood <oss@buserror.net>; > lkml <linux-kernel@vger.kernel.org>; open list:OPEN FIRMWARE AND > FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; Rob Herring > <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; linuxppc-dev > <linuxppc-dev@lists.ozlabs.org>; moderated list:ARM/FREESCALE IMX / MXC > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Michael Turquette > <mturquette@baylibre.com>; sboyd at kernel.org; Rafael J. Wysocki > <rjw@rjwysocki.net>; Viresh Kumar <viresh.kumar@linaro.org>; linux-clk <linux- > clk at vger.kernel.org>; linux-pm at vger.kernel.org; linux-kernel- > owner at vger.kernel.org; Catalin Marinas <catalin.marinas@arm.com>; Will > Deacon <will.deacon@arm.com>; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>; Kate > Stewart <kstewart@linuxfoundation.org>; yamada.masahiro at socionext.com; > Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Udit Kumar > <udit.kumar@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Ying Zhang > <ying.zhang22455@nxp.com>; Russell King <linux@armlinux.org.uk>; Ramneek > Mehresh <ramneek.mehresh@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; > Nipun Gupta <nipun.gupta@nxp.com>; Sriram Dash <sriram.dash@nxp.com> > Subject: Re: [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support > > On Mon, Sep 24, 2018 at 7:47 AM Vabhav Sharma <vabhav.sharma@nxp.com> > wrote: > > > > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. > > > > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor > > cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 > > I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 > > SBSA UARTs etc. > > > > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> > > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> > > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > > Signed-off-by: Sriram Dash <sriram.dash@nxp.com> > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 693 > > +++++++++++++++++++++++++ > > 1 file changed, 693 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > > new file mode 100644 > > index 0000000..46eea16 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi > > @@ -0,0 +1,693 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree > > +Include file for Layerscape-LX2160A family SoC. > > +// > > +// Copyright 2018 NXP > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > You included the header file, but you didn't use the MACROs in most of the > interrupts property below. It is recommended to use them for better readibity. Ok, I will update it. > > > + > > +/memreserve/ 0x80000000 0x00010000; > > + > > +/ { > > + compatible = "fsl,lx2160a"; > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + // 8 clusters having 2 Cortex-A72 cores each > > + cpu at 0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x0>; > > + clocks = <&clockgen 1 0>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster0_l2>; > > enable-method is a required property for this and cpu below. Ok > > > + }; > > + > > + cpu at 1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x1>; > > + clocks = <&clockgen 1 0>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster0_l2>; > > + }; > > + > > + cpu at 100 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x100>; > > + clocks = <&clockgen 1 1>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster1_l2>; > > + }; > > + > > + cpu at 101 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x101>; > > + clocks = <&clockgen 1 1>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster1_l2>; > > + }; > > + > > + cpu at 200 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x200>; > > + clocks = <&clockgen 1 2>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster2_l2>; > > + }; > > + > > + cpu at 201 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x201>; > > + clocks = <&clockgen 1 2>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster2_l2>; > > + }; > > + > > + cpu at 300 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x300>; > > + clocks = <&clockgen 1 3>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster3_l2>; > > + }; > > + > > + cpu at 301 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x301>; > > + clocks = <&clockgen 1 3>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster3_l2>; > > + }; > > + > > + cpu at 400 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x400>; > > + clocks = <&clockgen 1 4>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster4_l2>; > > + }; > > + > > + cpu at 401 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x401>; > > + clocks = <&clockgen 1 4>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster4_l2>; > > + }; > > + > > + cpu at 500 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x500>; > > + clocks = <&clockgen 1 5>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster5_l2>; > > + }; > > + > > + cpu at 501 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x501>; > > + clocks = <&clockgen 1 5>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster5_l2>; > > + }; > > + > > + cpu at 600 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x600>; > > + clocks = <&clockgen 1 6>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster6_l2>; > > + }; > > + > > + cpu at 601 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x601>; > > + clocks = <&clockgen 1 6>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster6_l2>; > > + }; > > + > > + cpu at 700 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x700>; > > + clocks = <&clockgen 1 7>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster7_l2>; > > + }; > > + > > + cpu at 701 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x701>; > > + clocks = <&clockgen 1 7>; > > + d-cache-size = <0x8000>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + i-cache-size = <0xC000>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <192>; > > + next-level-cache = <&cluster7_l2>; > > + }; > > + > > + cluster0_l2: l2-cache0 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster1_l2: l2-cache1 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster2_l2: l2-cache2 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster3_l2: l2-cache3 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster4_l2: l2-cache4 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster5_l2: l2-cache5 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster6_l2: l2-cache6 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + > > + cluster7_l2: l2-cache7 { > > + compatible = "cache"; > > + cache-size = <0x100000>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <2>; > > + }; > > + }; > > + > > + gic: interrupt-controller at 6000000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist > > + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + > > + // SGI_base) > > + <0x0 0x0c0c0000 0 0x2000>, // GICC > > + <0x0 0x0c0d0000 0 0x1000>, // GICH > > + <0x0 0x0c0e0000 0 0x20000>; // GICV > > + #interrupt-cells = <3>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + interrupt-controller; > > + interrupts = <1 9 0x4>; > > + > > + its: gic-its at 6020000 { > > + compatible = "arm,gic-v3-its"; > > + msi-controller; > > + reg = <0x0 0x6020000 0 0x20000>; > > + }; > > + }; > > + > > + rstcr: syscon at 1e60000 { > > + compatible = "syscon"; > > + reg = <0x0 0x1e60000 0x0 0x4>; > > + }; > > This is no use if you don't have a syscon-reboot node pointing to it. Agree, Thanks. > > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = <1 13 4>, > > + <1 14 4>, > > + <1 11 4>, > > + <1 10 4>; > > + }; > > + > > + pmu { > > + compatible = "arm,cortex-a72-pmu"; > > + interrupts = <1 7 0x8>; // PMU PPI, Level low type > > + }; > > + > > + psci { > > + compatible = "arm,psci-0.2"; > > + method = "smc"; > > + }; > > + > > + memory at 80000000 { > > + // DRAM space - 1, size : 2 GB DRAM > > + device_type = "memory"; > > + reg = <0x00000000 0x80000000 0 0x80000000>; > > + }; > > + > > + ddr1: memory-controller at 1080000 { > > + compatible = "fsl,qoriq-memory-controller"; > > + reg = <0x0 0x1080000 0x0 0x1000>; > > + interrupts = <0 17 0x4>; > > + little-endian; > > + }; > > + > > + ddr2: memory-controller at 1090000 { > > + compatible = "fsl,qoriq-memory-controller"; > > + reg = <0x0 0x1090000 0x0 0x1000>; > > + interrupts = <0 18 0x4>; > > + little-endian; > > + }; > > + > > + sysclk: sysclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <100000000>; > > + clock-output-names = "sysclk"; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clockgen: clocking at 1300000 { > > + compatible = "fsl,lx2160a-clockgen"; > > Also update the binding to include this new compatible. Ok,I will update clock/qoriq-clock.txt > > > + reg = <0 0x1300000 0 0xa0000>; > > + #clock-cells = <2>; > > + clocks = <&sysclk>; > > + }; > > + > > + crypto: crypto at 8000000 { > > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; > > + fsl,sec-era = <10>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0x00 0x8000000 0x100000>; > > + reg = <0x00 0x8000000 0x0 0x100000>; > > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; > > + dma-coherent; > > + status = "disabled"; > > + > > + sec_jr0: jr at 10000 { > > + compatible = "fsl,sec-v5.0-job-ring", > > + "fsl,sec-v4.0-job-ring"; > > + reg = <0x10000 0x10000>; > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + sec_jr1: jr at 20000 { > > + compatible = "fsl,sec-v5.0-job-ring", > > + "fsl,sec-v4.0-job-ring"; > > + reg = <0x20000 0x10000>; > > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + sec_jr2: jr at 30000 { > > + compatible = "fsl,sec-v5.0-job-ring", > > + "fsl,sec-v4.0-job-ring"; > > + reg = <0x30000 0x10000>; > > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + sec_jr3: jr at 40000 { > > + compatible = "fsl,sec-v5.0-job-ring", > > + "fsl,sec-v4.0-job-ring"; > > + reg = <0x40000 0x10000>; > > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > + dcfg: dcfg at 1e00000 { > > + compatible = "fsl,lx2160a-dcfg", "syscon"; > > Update the binding to include this new compatible. Sure, I will update arm/fsl.txt > > > + reg = <0x0 0x1e00000 0x0 0x10000>; > > + little-endian; > > + }; > > + > > + gpio0: gpio at 2300000 { > > + compatible = "fsl,qoriq-gpio"; > > + reg = <0x0 0x2300000 0x0 0x10000>; > > + interrupts = <0 36 0x4>; // Level high type > > + gpio-controller; > > + little-endian; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + }; > > + > > + gpio1: gpio at 2310000 { > > + compatible = "fsl,qoriq-gpio"; > > + reg = <0x0 0x2310000 0x0 0x10000>; > > + interrupts = <0 36 0x4>; // Level high type > > + gpio-controller; > > + little-endian; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + }; > > + > > + gpio2: gpio at 2320000 { > > + compatible = "fsl,qoriq-gpio"; > > + reg = <0x0 0x2320000 0x0 0x10000>; > > + interrupts = <0 37 0x4>; // Level high type > > + gpio-controller; > > + little-endian; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + }; > > + > > + gpio3: gpio at 2330000 { > > + compatible = "fsl,qoriq-gpio"; > > + reg = <0x0 0x2330000 0x0 0x10000>; > > + interrupts = <0 37 0x4>; // Level high type > > + gpio-controller; > > + little-endian; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + }; > > + > > + > > One new line is enough. Ok > > > + i2c0: i2c at 2000000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2000000 0x0 0x10000>; > > + interrupts = <0 34 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + fsl-scl-gpio = <&gpio2 15 0>; > > + status = "disabled"; > > + }; > > + > > + i2c1: i2c at 2010000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2010000 0x0 0x10000>; > > + interrupts = <0 34 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + status = "disabled"; > > + }; > > + > > + i2c2: i2c at 2020000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2020000 0x0 0x10000>; > > + interrupts = <0 35 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + status = "disabled"; > > + }; > > + > > + i2c3: i2c at 2030000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2030000 0x0 0x10000>; > > + interrupts = <0 35 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + status = "disabled"; > > + }; > > + > > + i2c4: i2c at 2040000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2040000 0x0 0x10000>; > > + interrupts = <0 74 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + fsl-scl-gpio = <&gpio2 16 0>; > > + status = "disabled"; > > + }; > > + > > + i2c5: i2c at 2050000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2050000 0x0 0x10000>; > > + interrupts = <0 74 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + status = "disabled"; > > + }; > > + > > + i2c6: i2c at 2060000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2060000 0x0 0x10000>; > > + interrupts = <0 75 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + status = "disabled"; > > + }; > > + > > + i2c7: i2c at 2070000 { > > + compatible = "fsl,vf610-i2c"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x0 0x2070000 0x0 0x10000>; > > + interrupts = <0 75 0x4>; // Level high type > > + clock-names = "i2c"; > > + clocks = <&clockgen 4 7>; > > + status = "disabled"; > > + }; > > + > > + uart0: serial at 21c0000 { > > + device_type = "serial"; > > + compatible = "arm,pl011","arm,sbsa-uart"; > > From the sbsa_uart binding: > This UART uses a subset of the PL011 registers and consequently lives in the > PL011 driver. It's baudrate and other communication parameters cannot be > adjusted at runtime, so it lacks a clock specifier here. > > So it is a more specific variant of pl011. Put the sbsa-uart compatible first. Ok. > > > + reg = <0x0 0x21c0000 0x0 0x1000>; > > + interrupts = <0 32 0x4>; // Level high type > > + current-speed = <115200>; > > + status = "disabled"; > > + }; > > + > > + uart1: serial at 21d0000 { > > + device_type = "serial"; > > + compatible = "arm,pl011","arm,sbsa-uart"; > > + reg = <0x0 0x21d0000 0x0 0x1000>; > > + interrupts = <0 33 0x4>; // Level high type > > + current-speed = <115200>; > > + status = "disabled"; > > + }; > > + > > + uart2: serial at 21e0000 { > > + device_type = "serial"; > > + compatible = "arm,pl011","arm,sbsa-uart"; > > + reg = <0x0 0x21e0000 0x0 0x1000>; > > + interrupts = <0 72 0x4>; // Level high type > > + current-speed = <115200>; > > + status = "disabled"; > > + }; > > + > > + uart3: serial at 21f0000 { > > + device_type = "serial"; > > + compatible = "arm,pl011","arm,sbsa-uart"; > > + reg = <0x0 0x21f0000 0x0 0x1000>; > > + interrupts = <0 73 0x4>; // Level high type > > + current-speed = <115200>; > > + status = "disabled"; > > + }; > > + > > + smmu: iommu at 5000000 { > > + compatible = "arm,mmu-500"; > > + reg = <0 0x5000000 0 0x800000>; > > + #iommu-cells = <1>; > > + #global-interrupts = <14>; > > + interrupts = <0 13 4>, // global secure fault > > + <0 14 4>, // combined secure interrupt > > + <0 15 4>, // global non-secure fault > > + <0 16 4>, // combined non-secure interrupt > > + // performance counter interrupts 0-9 > > + <0 211 4>, <0 212 4>, > > + <0 213 4>, <0 214 4>, > > + <0 215 4>, <0 216 4>, > > + <0 217 4>, <0 218 4>, > > + <0 219 4>, <0 220 4>, > > + // per context interrupt, 64 interrupts > > + <0 146 4>, <0 147 4>, > > + <0 148 4>, <0 149 4>, > > + <0 150 4>, <0 151 4>, > > + <0 152 4>, <0 153 4>, > > + <0 154 4>, <0 155 4>, > > + <0 156 4>, <0 157 4>, > > + <0 158 4>, <0 159 4>, > > + <0 160 4>, <0 161 4>, > > + <0 162 4>, <0 163 4>, > > + <0 164 4>, <0 165 4>, > > + <0 166 4>, <0 167 4>, > > + <0 168 4>, <0 169 4>, > > + <0 170 4>, <0 171 4>, > > + <0 172 4>, <0 173 4>, > > + <0 174 4>, <0 175 4>, > > + <0 176 4>, <0 177 4>, > > + <0 178 4>, <0 179 4>, > > + <0 180 4>, <0 181 4>, > > + <0 182 4>, <0 183 4>, > > + <0 184 4>, <0 185 4>, > > + <0 186 4>, <0 187 4>, > > + <0 188 4>, <0 189 4>, > > + <0 190 4>, <0 191 4>, > > + <0 192 4>, <0 193 4>, > > + <0 194 4>, <0 195 4>, > > + <0 196 4>, <0 197 4>, > > + <0 198 4>, <0 199 4>, > > + <0 200 4>, <0 201 4>, > > + <0 202 4>, <0 203 4>, > > + <0 204 4>, <0 205 4>, > > + <0 206 4>, <0 207 4>, > > + <0 208 4>, <0 209 4>; > > + dma-coherent; > > + }; > > + > > + usb0: usb3 at 3100000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0x3100000 0x0 0x10000>; > > + interrupts = <0 80 0x4>; // Level high type > > + dr_mode = "host"; > > + snps,quirk-frame-length-adjustment = <0x20>; > > + snps,dis_rxdet_inp3_quirk; > > + status = "disabled"; > > + }; > > + > > + usb1: usb3 at 3110000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0x3110000 0x0 0x10000>; > > + interrupts = <0 81 0x4>; // Level high type > > + dr_mode = "host"; > > + snps,quirk-frame-length-adjustment = <0x20>; > > + snps,dis_rxdet_inp3_quirk; > > + status = "disabled"; > > + }; > > + > > + watchdog at 23a0000 { > > + compatible = "arm,sbsa-gwdt"; > > + reg = <0x0 0x23a0000 0 0x1000>, > > + <0x0 0x2390000 0 0x1000>; > > + interrupts = <0 59 4>; > > + timeout-sec = <30>; > > + }; > > + > > No new line is needed here. Ok > > > + }; > > +}; > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma ` (4 preceding siblings ...) 2018-09-24 0:09 ` [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma @ 2018-09-24 0:09 ` Vabhav Sharma 2018-09-28 19:37 ` Li Yang 5 siblings, 1 reply; 16+ messages in thread From: Vabhav Sharma @ 2018-09-24 0:09 UTC (permalink / raw) To: linux-arm-kernel LX2160A reference design board (RDB) is a high-performance computing, evaluation, and development platform with LX2160A SoC. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 88 +++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 86e18ad..445b72b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts new file mode 100644 index 0000000..1bbe663 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2160ARDB +// +// Copyright 2018 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ARDB"; + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-mux at 77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor at 40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + }; + + i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temperature-sensor at 4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + }; + + temperature-sensor at 4d { + compatible = "nxp,sa56004"; + reg = <0x4d>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + rtc at 51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + // IRQ10_B + interrupts = <0 150 0x4>; + }; + +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support 2018-09-24 0:09 ` [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support Vabhav Sharma @ 2018-09-28 19:37 ` Li Yang 2018-10-01 12:26 ` Vabhav Sharma 0 siblings, 1 reply; 16+ messages in thread From: Li Yang @ 2018-09-28 19:37 UTC (permalink / raw) To: linux-arm-kernel On Mon, Sep 24, 2018 at 7:51 AM Vabhav Sharma <vabhav.sharma@nxp.com> wrote: > > LX2160A reference design board (RDB) is a high-performance > computing, evaluation, and development platform with LX2160A > SoC. Please send next version with Shawn Guo and me in the "to" recipient so that its less likely we will miss it. > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 88 +++++++++++++++++++++++ > 2 files changed, 89 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 86e18ad..445b72b 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > new file mode 100644 > index 0000000..1bbe663 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > @@ -0,0 +1,88 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +// > +// Device Tree file for LX2160ARDB > +// > +// Copyright 2018 NXP > + > +/dts-v1/; > + > +#include "fsl-lx2160a.dtsi" > + > +/ { > + model = "NXP Layerscape LX2160ARDB"; > + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > + i2c-mux at 77 { > + compatible = "nxp,pca9547"; > + reg = <0x77>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + i2c at 2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x2>; > + > + power-monitor at 40 { > + compatible = "ti,ina220"; > + reg = <0x40>; > + shunt-resistor = <1000>; > + }; > + }; > + > + i2c at 3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + > + temperature-sensor at 4c { > + compatible = "nxp,sa56004"; > + reg = <0x4c>; Need a vcc-supply property according to the binding. > + }; > + > + temperature-sensor at 4d { > + compatible = "nxp,sa56004"; > + reg = <0x4d>; Ditto. > + }; > + }; > + }; > +}; > + > +&i2c4 { > + status = "okay"; > + > + rtc at 51 { > + compatible = "nxp,pcf2129"; > + reg = <0x51>; > + // IRQ10_B > + interrupts = <0 150 0x4>; > + }; > + > +}; > + > +&usb0 { > + status = "okay"; > +}; > + > +&usb1 { > + status = "okay"; > +}; > + > +&crypto { > + status = "okay"; > +}; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support 2018-09-28 19:37 ` Li Yang @ 2018-10-01 12:26 ` Vabhav Sharma 0 siblings, 0 replies; 16+ messages in thread From: Vabhav Sharma @ 2018-10-01 12:26 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: devicetree-owner at vger.kernel.org <devicetree-owner@vger.kernel.org> > On Behalf Of Li Yang > Sent: Saturday, September 29, 2018 1:07 AM > To: Vabhav Sharma <vabhav.sharma@nxp.com> > Cc: Sudeep Holla <sudeep.holla@arm.com>; Scott Wood <oss@buserror.net>; > lkml <linux-kernel@vger.kernel.org>; open list:OPEN FIRMWARE AND > FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; Rob Herring > <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; linuxppc-dev > <linuxppc-dev@lists.ozlabs.org>; moderated list:ARM/FREESCALE IMX / MXC > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Michael Turquette > <mturquette@baylibre.com>; sboyd at kernel.org; Rafael J. Wysocki > <rjw@rjwysocki.net>; Viresh Kumar <viresh.kumar@linaro.org>; linux-clk <linux- > clk at vger.kernel.org>; linux-pm at vger.kernel.org; linux-kernel- > owner at vger.kernel.org; Catalin Marinas <catalin.marinas@arm.com>; Will > Deacon <will.deacon@arm.com>; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>; Kate > Stewart <kstewart@linuxfoundation.org>; yamada.masahiro at socionext.com; > Udit Kumar <udit.kumar@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; > Russell King <linux@armlinux.org.uk>; Varun Sethi <V.Sethi@nxp.com>; Sriram > Dash <sriram.dash@nxp.com> > Subject: Re: [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support > > On Mon, Sep 24, 2018 at 7:51 AM Vabhav Sharma <vabhav.sharma@nxp.com> > wrote: > > > > LX2160A reference design board (RDB) is a high-performance computing, > > evaluation, and development platform with LX2160A SoC. > > Please send next version with Shawn Guo and me in the "to" recipient so that its > less likely we will miss it. My mistake, Not Sure how it's missed. > > > > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > > Signed-off-by: Sriram Dash <sriram.dash@nxp.com> > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/Makefile | 1 + > > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 88 > > +++++++++++++++++++++++ > > 2 files changed, 89 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > > b/arch/arm64/boot/dts/freescale/Makefile > > index 86e18ad..445b72b 100644 > > --- a/arch/arm64/boot/dts/freescale/Makefile > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a- > rdb.dtb > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb > > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > > new file mode 100644 > > index 0000000..1bbe663 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts > > @@ -0,0 +1,88 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree file > > +for LX2160ARDB // // Copyright 2018 NXP > > + > > +/dts-v1/; > > + > > +#include "fsl-lx2160a.dtsi" > > + > > +/ { > > + model = "NXP Layerscape LX2160ARDB"; > > + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > + > > +&uart1 { > > + status = "okay"; > > +}; > > + > > +&i2c0 { > > + status = "okay"; > > + i2c-mux at 77 { > > + compatible = "nxp,pca9547"; > > + reg = <0x77>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + i2c at 2 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x2>; > > + > > + power-monitor at 40 { > > + compatible = "ti,ina220"; > > + reg = <0x40>; > > + shunt-resistor = <1000>; > > + }; > > + }; > > + > > + i2c at 3 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x3>; > > + > > + temperature-sensor at 4c { > > + compatible = "nxp,sa56004"; > > + reg = <0x4c>; > > Need a vcc-supply property according to the binding. Ok > > > + }; > > + > > + temperature-sensor at 4d { > > + compatible = "nxp,sa56004"; > > + reg = <0x4d>; > > Ditto. Ok > > > + }; > > + }; > > + }; > > +}; > > + > > +&i2c4 { > > + status = "okay"; > > + > > + rtc at 51 { > > + compatible = "nxp,pcf2129"; > > + reg = <0x51>; > > + // IRQ10_B > > + interrupts = <0 150 0x4>; > > + }; > > + > > +}; > > + > > +&usb0 { > > + status = "okay"; > > +}; > > + > > +&usb1 { > > + status = "okay"; > > +}; > > + > > +&crypto { > > + status = "okay"; > > +}; > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2018-10-03 14:25 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-09-24 0:08 [PATCH v3 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 1/6] dt-bindings: arm64: add compatible for LX2160A Vabhav Sharma 2018-09-27 19:32 ` Rob Herring 2018-09-24 0:08 ` [PATCH v3 2/6] soc/fsl/guts: Add compatible string " Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 3/6] drivers: clk-qoriq: increase array size of cmux_to_group Vabhav Sharma 2018-10-01 22:04 ` Stephen Boyd 2018-10-03 14:25 ` Vabhav Sharma 2018-09-24 0:08 ` [PATCH v3 4/6] drivers: clk-qoriq: Add clockgen support for lx2160a Vabhav Sharma 2018-10-01 22:04 ` Stephen Boyd 2018-10-03 14:25 ` Vabhav Sharma 2018-09-24 0:09 ` [PATCH v3 5/6] arm64: dts: add QorIQ LX2160A SoC support Vabhav Sharma 2018-09-28 20:41 ` Li Yang 2018-10-01 12:19 ` Vabhav Sharma 2018-09-24 0:09 ` [PATCH v3 6/6] arm64: dts: add LX2160ARDB board support Vabhav Sharma 2018-09-28 19:37 ` Li Yang 2018-10-01 12:26 ` Vabhav Sharma
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