From: joel@joelfernandes.org (Joel Fernandes (Google))
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 7/7] dmaengine: stm32-dma: properly mask irq bits
Date: Mon, 8 Oct 2018 22:47:52 -0700 [thread overview]
Message-ID: <20181009054752.145978-8-joel@joelfernandes.org> (raw)
In-Reply-To: <20181009054752.145978-1-joel@joelfernandes.org>
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
A single register of the controller holds the information for four dma
channels.
The functions stm32_dma_irq_status() don't mask the relevant bits after
the shift, thus adjacent channel's status is also reported in the returned
value.
Fixed by masking the value before returning it.
Similarly, the function stm32_dma_irq_clear() don't mask the input value
before shifting it, thus an incorrect input value could disable the
interrupts of adjacent channels.
Fixed by masking the input value before using it.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 05a2974cd2c0..8c5807362a25 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -38,6 +38,10 @@
#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
+#define STM32_DMA_MASKI (STM32_DMA_TCI \
+ | STM32_DMA_TEI \
+ | STM32_DMA_DMEI \
+ | STM32_DMA_FEI)
/* DMA Stream x Configuration Register */
#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
@@ -405,7 +409,7 @@ static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
- return flags;
+ return flags & STM32_DMA_MASKI;
}
static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
@@ -420,6 +424,7 @@ static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
* If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
* If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
*/
+ flags &= STM32_DMA_MASKI;
dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
if (chan->id & 4)
--
2.19.0.605.g01d371f741-goog
next prev parent reply other threads:[~2018-10-09 5:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-09 5:47 [PATCH 0/7] NULL pointer deref fix for stm32-dma Joel Fernandes (Google)
2018-10-09 5:47 ` [PATCH 1/7] dmaengine: stm32-dma: threshold manages with bitfield feature Joel Fernandes (Google)
2018-10-09 5:47 ` [PATCH 2/7] dmaengine: stm32-dma: fix incomplete configuration in cyclic mode Joel Fernandes (Google)
2018-10-09 5:47 ` [PATCH 3/7] dmaengine: stm32-dma: fix typo and reported checkpatch warnings Joel Fernandes (Google)
2018-10-09 5:47 ` [PATCH 4/7] dmaengine: stm32-dma: Improve memory burst management Joel Fernandes (Google)
2018-10-09 5:47 ` [PATCH 5/7] dmaengine: stm32-dma: fix DMA IRQ status handling Joel Fernandes (Google)
2018-10-09 5:47 ` [PATCH 6/7] dmaengine: stm32-dma: fix max items per transfer Joel Fernandes (Google)
2018-10-09 5:47 ` Joel Fernandes (Google) [this message]
2018-10-15 17:00 ` [PATCH 0/7] NULL pointer deref fix for stm32-dma Vinod
2018-10-16 16:11 ` Greg KH
2018-10-16 23:49 ` Joel Fernandes
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