From mboxrd@z Thu Jan 1 00:00:00 1970 From: jagan@amarulasolutions.com (Jagan Teki) Date: Tue, 13 Nov 2018 16:46:29 +0530 Subject: [PATCH v4 22/26] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI In-Reply-To: <20181113111633.20189-1-jagan@amarulasolutions.com> References: <20181113111633.20189-1-jagan@amarulasolutions.com> Message-ID: <20181113111633.20189-23-jagan@amarulasolutions.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz, but lowering the min rate by 300MHz can result proper working nkms divider with the help of desired dclock rate from panel driver. Signed-off-by: Jagan Teki Acked-by: Stephen Boyd --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 019d67bf97c4..5a3a5b821f8b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = { .n = _SUNXI_CCU_MULT(8, 4), .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), .m = _SUNXI_CCU_DIV(0, 4), + .min_rate = 300000000, /* Actual rate is 500MHz */ + .max_rate = 1400000000UL, .common = { .reg = 0x040, .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", -- 2.18.0.321.gffc6fa0e3