[PATCH v3] ARM: dts: sun8i: Add the H3/H5 CSI controller

[maxime.ripard@bootlin.com (Maxime Ripard)]

On Tue, Nov 27, 2018 at 01:36:38PM +0530, Jagan Teki wrote:
> On Tue, Nov 27, 2018 at 1:24 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Nov 27, 2018 at 11:29:13AM +0530, Jagan Teki wrote:
> > > On Tue, Nov 20, 2018 at 9:53 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > > >
> > > > From: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > > >
> > > > The H3 and H5 features the same CSI controller that was initially found on
> > > > the A31.
> > > >
> > > > Add a DT node for it.
> > > >
> > > > Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > > >
> > > > ---
> > > >
> > > > Changes from v3:
> > > >   - Removed the CSI MCLK pin from the default pin group
> > >
> > > If I'm not wrong, PE1 is CSI_MCLK and PE0 is CSI_PCLK so we have PE0
> > > and PE1 removed.
> >
> > i'm not sure what you mean, PCLK is still in that patch.
> 
> PE0 -> CSI_PCLK
> PE1 -> CSI_MCLK
> 
> So, removing CSI MCLK in "Changes from v3" means, removing PE1 right?
> but csi_pins removed PE0 which is CSI_PCLK, we need to remove PE1 from
> csi_pins and keep PE0. isn't it?

Ah, right. I've fixed it up while applying.

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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