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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id c23sm20174078pfi.83.2018.12.03.08.09.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:09:08 -0800 (PST) Date: Mon, 3 Dec 2018 08:09:05 -0800 From: Bjorn Andersson To: Jeffrey Hugo Subject: Re: WIP: UFS on apq8098 Message-ID: <20181203160905.GR2225@minitux> References: <7d588806-5699-2d87-e95e-f1388de01a74@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <7d588806-5699-2d87-e95e-f1388de01a74@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181203_080920_746358_0CDA3592 X-CRM114-Status: GOOD ( 21.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rajendra Nayak , Marc Gonzalez , MSM , Niklas Cassel , Nicolas Dechesne , Andy Gross , Linux ARM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon 03 Dec 07:47 PST 2018, Jeffrey Hugo wrote: > On 12/3/2018 8:27 AM, Jeffrey Hugo wrote: > > On 12/3/2018 8:18 AM, Marc Gonzalez wrote: > > > Hello, > > > = > > > I'm trying to enable UFS on apq8098. Just wanted to share my progress > > > so far, in case someone spots any glaring mistakes. > > = > > Excellent.=A0 This was down on my todo list.=A0 I'm glad its getting so= me > > attention. > > = > > > = > > > (WIP patch provided at message's end.) > > > = > > > rpm_smd_clk_probe() runs successfully, and returns 0. > > > = > > > qcom_qmp_phy_probe() fails: > > > = > > > [=A0=A0=A0 0.913707] qcom-qmp-phy 1da7000.phy: Failed to get clk 'ref= ': -2 > > > [=A0=A0=A0 0.913761] qcom-qmp-phy: probe of 1da7000.phy failed with e= rror -2 > > > = > > > ufs_qcom_probe() also fails (which may be caused by PHY failure) > > > = > > > [=A0=A0=A0 2.368486] ufshcd-qcom 1da4000.ufshc: ufshcd_get_vreg: vdd-= hba > > > get failed, err=3D-517 > > > [=A0=A0=A0 2.370673] ufshcd-qcom 1da4000.ufshc: Initialization failed > > > [=A0=A0=A0 2.412908] ufshcd-qcom 1da4000.ufshc: ufshcd_pltfrm_init() > > > failed -517 > > > = > > > I'll investigate the PHY init. > > > = > > > Regards. > > > = > > > = > > > diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > > > b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > > > index b4276da1fb0d..ad7542f461af 100644 > > > --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi > > > @@ -241,3 +241,26 @@ > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0 }; > > > =A0=A0=A0=A0=A0 }; > > > =A0 }; > > > + > > > +&ufshc { > > > +=A0=A0=A0 status =3D "ok"; > > > +=A0=A0=A0 vdd-hba-supply =3D <&gcc UFS_GDSC>; > > > +=A0=A0=A0 vdd-hba-fixed-regulator; > > > +=A0=A0=A0 vcc-supply =3D <&vreg_l20a_2p95>; > > > +=A0=A0=A0 vccq-supply =3D <&vreg_l26a_1p2>; > > > +=A0=A0=A0 vccq2-supply =3D <&vreg_s4a_1p8>; > > > +=A0=A0=A0 vcc-max-microamp =3D <750000>; > > > +=A0=A0=A0 vccq-max-microamp =3D <560000>; > > > +=A0=A0=A0 vccq2-max-microamp =3D <750000>; > > > +}; > > > + > > > +&ufsphy { > > > +=A0=A0=A0 status =3D "ok"; > > > +=A0=A0=A0 vdda-phy-supply =3D <&vreg_l1a_0p875>; > > > +=A0=A0=A0 vdda-pll-supply =3D <&vreg_l2a_1p2>; > > > +=A0=A0=A0 vddp-ref-clk-supply =3D <&vreg_l26a_1p2>; > > > +=A0=A0=A0 vdda-phy-max-microamp =3D <51400>; > > > +=A0=A0=A0 vdda-pll-max-microamp =3D <14600>; > > > +=A0=A0=A0 vddp-ref-clk-max-microamp =3D <100>; > > > +=A0=A0=A0 vddp-ref-clk-always-on; > > > +}; > > > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi > > > b/arch/arm64/boot/dts/qcom/msm8998.dtsi > > > index d291b4713c33..10e7b8a55b8a 100644 > > > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > > > @@ -264,6 +264,11 @@ > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0 rpm_requests: rpm-requests { > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 compatible =3D "qcom,rpm-msm8= 998"; > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 qcom,glink-channels =3D "rpm_= requests"; > > > + > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 rpmcc: qcom,rpmcc { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 compatible =3D "qcom,r= pmcc-msm8998"; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 #clock-cells =3D <1>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 }; > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0 }; > > > =A0=A0=A0=A0=A0 }; > > > @@ -686,5 +691,79 @@ > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 redistributor-stride =3D <0x0= 0x20000>; > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 interrupts =3D ; > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0 }; > > > + > > > +=A0=A0=A0=A0=A0=A0=A0 ufshc: ufshc@1da4000 { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 compatible =3D "qcom,msm8998-ufshc= ", "qcom,ufshc", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "jedec,= ufs-2.0"; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 reg =3D <0x1da4000 0x2500>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 interrupts =3D ; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 phys =3D <&ufsphy_lanes>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 phy-names =3D "ufsphy"; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 lanes-per-direction =3D <2>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 power-domains =3D <&gcc UFS_GDSC>; > > > + > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 clock-names =3D > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "core_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "bus_aggr_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "iface_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "core_clk_unipro", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "core_clk_ice", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "ref_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "tx_lane0_sync_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "rx_lane0_sync_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "rx_lane1_sync_clk"; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 clocks =3D > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_AXI_CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_AGGRE1_UFS_A= XI_CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_AHB_CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_UNIPRO_C= ORE_CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_ICE_CORE= _CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&rpmcc 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_TX_SYMBO= L_0_CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_RX_SYMBO= L_0_CLK>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_RX_SYMBO= L_1_CLK>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 freq-table-hz =3D > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <50000000 200000000>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <0 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <0 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <37500000 150000000>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <75000000 300000000>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <0 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <0 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <0 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <0 0>; > > > + > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 resets =3D <&gcc GCC_UFS_BCR>; > > = > > I dunno how much this factors into your issues, but the resets defined > > in gcc-msm8998.c are wrong.=A0 I'm posting a patch later today.=A0 I kn= ow > > this was a problem for me with USB. > > = > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 reset-names =3D "rst"; > > > + > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 status =3D "disabled"; > > > +=A0=A0=A0=A0=A0=A0=A0 }; > > > + > > > +=A0=A0=A0=A0=A0=A0=A0 ufsphy: phy@1da7000 { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 compatible =3D "qcom,sdm845-qmp-uf= s-phy"; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 reg =3D <0x1da7000 0x18c>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 #address-cells =3D <1>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 #size-cells =3D <1>; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 ranges; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 clock-names =3D > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "ref_clk_src", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "ref_clk", > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 "ref_aux_clk"; > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 clocks =3D > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&rpmcc 0>, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 <&gcc GCC_UFS_CLKREF_C= LK>, > = > Also, "GCC_UFS_CLKREF_CLK" is not defined in > include/dt-bindings/clock/qcom,gcc-msm8998.h which is probably the cause = of > your -2 error listed above. > = I agree, this would cause the problem you're seeing. Please find this clock at: https://lore.kernel.org/lkml/20181130065259.26497-4-bjorn.andersson@linaro.= org/ I will respin patch 1 and post the series again in a few hours. Regards, Bjorn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel