[PATCH V5 0/6] ARM: imx: add imx7ulp support

[PATCH V5 0/6] ARM: imx: add imx7ulp support

[A.s. Dong]

The i.MX 7ULP family of processors represents NXP?s latest achievement
in ultra-low-power processing for use cases demanding long battery life.
Targeted towards the growing market of portable devices, the i.MX 7ULP
family of processors features NXP's advanced implementation of the Arm?
Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit
LPDDR2/LPDDR3 memory interface and a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and
camera sensors.

This patch series adds the basic support for imx7ulp. It includes machine
level support code and device tree.
Note: it depends on clk driver which is still under review.

v4->v5:
 * dts add input clocks for PCC module
 * update pad setting due to missing pull up enabled
   (formerly auto done by driver generic pinconfg)
 * gpio and pinctrl patches were merged by Linus W, so dropped in this series
  dt-bindings: gpio: vf610: add optional clocks property
  gpio: vf610: add optional clock support
  dt-bindings: pinctrl: imx7ulp: back to imx legacy binding for
    consistency
  pinctrl: fsl: imx7ulp: change to use imx legacy binding

v3->v4:
 * add comments about fixed soc version
 * add iounmap
v2->v3:
 * back to old pinctrl binding according to SoC maintainer's suggestions
 * use generic node name
 * error checking updated according to Russell's suggestion:
   ptr == ERR_PTR(-EPROBE_DEFER)

v1->v2:
 * switch to SPDX license
 * rebase to latest tree
 * pad name update
 * add gpio clk support
 * minor fix



Dong Aisheng (6):
  dt-bindings: fsl: add compatible for imx7ulp evk
  dt-bindings: fsl: add imx7ulp pm related components bindings
  ARM: imx: add initial support for imx7ulp
  dts: imx: add common imx7ulp dtsi support
  dts: fsl: add imx7ulp evk support
  ARM: imx_v6_v7_defconfig: add imx7ulp support

 .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      |  23 ++
 Documentation/devicetree/bindings/arm/fsl.txt      |   8 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts                  |  77 +++++
 arch/arm/boot/dts/imx7ulp.dtsi                     | 346 +++++++++++++++++++++
 arch/arm/configs/imx_v6_v7_defconfig               |   1 +
 arch/arm/mach-imx/Kconfig                          |   9 +
 arch/arm/mach-imx/Makefile                         |   1 +
 arch/arm/mach-imx/common.h                         |   1 +
 arch/arm/mach-imx/cpu.c                            |   3 +
 arch/arm/mach-imx/mach-imx7ulp.c                   |  33 ++
 arch/arm/mach-imx/mxc.h                            |   1 +
 arch/arm/mach-imx/pm-imx7ulp.c                     |  29 ++
 13 files changed, 534 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

-- 
2.7.4

[PATCH V5 1/6] dt-bindings: fsl: add compatible for imx7ulp evk

[A.s. Dong]

Cc: devicetree at vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 7b964d8..9c7c788 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -101,6 +101,10 @@ i.MX7 SabreSD Board
 Required root node properties:
     - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
+i.MX7ULP Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
 Generic i.MX boards
 -------------------
 
@@ -123,6 +127,10 @@ i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
 
+i.MX7ULP generic board
+Required root node properties:
+    - compatible = "fsl,imx7ulp";
+
 Freescale Vybrid Platform Device Tree Bindings
 ----------------------------------------------
 
-- 
2.7.4

[PATCH V5 2/6] dt-bindings: fsl: add imx7ulp pm related components bindings

[A.s. Dong]

Add imx7ulp pm related components bindings

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
 * no changes
v1->v2:
 * new patch
---
 .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
new file mode 100644
index 0000000..75195be
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
@@ -0,0 +1,23 @@
+Freescale i.MX7ULP Power Management Components
+----------------------------------------------
+
+The Multi-System Mode Controller (MSMC) is responsible for sequencing
+the MCU into and out of all stop and run power modes. Specifically, it
+monitors events to trigger transitions between power modes while
+controlling the power, clocks, and memories of the MCU to achieve the
+power consumption and functionality of that mode.
+
+The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
+Standby modes for either Cortex family. Run, Wait, and Stop are the
+common terms used for the primary operating modes of Kinetis
+microcontrollers.
+
+Required properties:
+- compatible:	Should be "fsl,imx7ulp-smc1".
+- reg:		Specifies base physical address and size of the register sets.
+
+Example:
+smc1: smc1 at 40410000 {
+	compatible = "fsl,imx7ulp-smc1";
+	reg = <0x40410000 0x1000>;
+};
-- 
2.7.4

[PATCH V5 3/6] ARM: imx: add initial support for imx7ulp

[A.s. Dong]

The i.MX 7ULP family of processors features NXP's advanced implementation
of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
Graphics Processing Units (GPUs).

This patch aims to add an initial support for imx7ulp. Note that we need
configure power mode to Partial Stop mode 3 with system/bus clock enabled
first as the default enabled STOP mode will gate off system/bus clock when
execute WFI in MX7ULP SoC.

And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no
anatop as before. So we encode one with 0xff in reverse order in case new
ones will be in the future.

Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v3->v4:
 * add iounmap(smc1_base)
 * add comments about fixed SoC version
v2->v3:
 * no changes
v1->v2:
 * switch to SPDX license
 * more description of new SOC in commit message
---
 arch/arm/mach-imx/Kconfig        |  9 +++++++++
 arch/arm/mach-imx/Makefile       |  1 +
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/cpu.c          |  3 +++
 arch/arm/mach-imx/mach-imx7ulp.c | 33 +++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mxc.h          |  1 +
 arch/arm/mach-imx/pm-imx7ulp.c   | 29 +++++++++++++++++++++++++++++
 7 files changed, 77 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index abc3371..c12a05c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -558,6 +558,15 @@ config SOC_IMX7D
 	help
 		This enables support for Freescale i.MX7 Dual processor.
 
+config SOC_IMX7ULP
+	bool "i.MX7ULP support"
+	select ARM_GIC
+	select CLKSRC_IMX_TPM
+	select HAVE_ARM_ARCH_TIMER
+	select PINCTRL_IMX7ULP
+	help
+	  This enables support for Freescale i.MX7 Ultra Low Power processor.
+
 config SOC_VF610
 	bool "Vybrid Family VF610 support"
 	select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bae179a..8af2f7e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
 obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
 obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
 
 ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 423dd76..bc915e5 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -120,6 +120,7 @@ void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
 void imx6sx_pm_init(void);
 void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
 
 #ifdef CONFIG_PM
 void imx51_pm_init(void);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index c73593e..0b137ee 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -145,6 +145,9 @@ struct device * __init imx_soc_device_init(void)
 	case MXC_CPU_IMX7D:
 		soc_id = "i.MX7D";
 		break;
+	case MXC_CPU_IMX7ULP:
+		soc_id = "i.MX7ULP";
+		break;
 	default:
 		soc_id = "Unknown";
 	}
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
new file mode 100644
index 0000000..979ad02
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Author: Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+	imx7ulp_pm_init();
+
+	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+	/* FIXME: so far there is still no way to retrieve SoC version */
+	imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_UNKNOWN);
+	of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+	"fsl,imx7ulp",
+	NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+	.init_machine	= imx7ulp_init_machine,
+	.dt_compat	= imx7ulp_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index b130a53..8e72d4e 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -44,6 +44,7 @@
 #define MXC_CPU_IMX6ULZ		0x6b
 #define MXC_CPU_IMX6SLL		0x67
 #define MXC_CPU_IMX7D		0x72
+#define MXC_CPU_IMX7ULP		0xff
 
 #define IMX_DDR_TYPE_LPDDR2		1
 
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
new file mode 100644
index 0000000..cf6a380
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Author: Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL		0x10
+#define BP_PMCTRL_PSTOPO        16
+#define PSTOPO_PSTOP3		0x3
+
+void __init imx7ulp_pm_init(void)
+{
+	struct device_node *np;
+	void __iomem *smc1_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+	smc1_base = of_iomap(np, 0);
+	WARN_ON(!smc1_base);
+
+	/* Partial Stop mode 3 with system/bus clock enabled */
+	writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
+		       smc1_base + SMC_PMCTRL);
+	iounmap(smc1_base);
+}
-- 
2.7.4

[PATCH V5 4/6] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

The i.MX 7ULP family of processors features NXP's advanced implementation
of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
Graphics Processing Units (GPUs).

This patch aims to add the initial support including:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v4->v5:
 * add input clocks for PCC module
v3->v4:
 * no changes
v2->v3:
 * change to generic node names
 * remove arch timer due to:
   1) arch timer is fixed to 1Mhz which is lower accurate than TPM timer (3Mhz).
   2) no firmware progrem CNTFREQ
   3) cpuidle driver is still not in tree will may cause system hang
v1->v2:
 * update clk part due to binding change
 * separate soc.dtsi from board.dts
---
 arch/arm/boot/dts/imx7ulp.dtsi | 346 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 346 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..931b275
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	intc: interrupt-controller at 40021000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x40021000 0x1000>,
+		      <0x40022000 0x1000>;
+	};
+
+	rosc: clock-rosc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "rosc";
+		#clock-cells = <0>;
+	};
+
+	sosc: clock-sosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "sosc";
+		#clock-cells = <0>;
+	};
+
+	sirc: clock-sirc {
+		compatible = "fixed-clock";
+		clock-frequency = <16000000>;
+		clock-output-names = "sirc";
+		#clock-cells = <0>;
+	};
+
+	firc: clock-firc {
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+		clock-output-names = "firc";
+		#clock-cells = <0>;
+	};
+
+	upll: clock-upll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "upll";
+		#clock-cells = <0>;
+	};
+
+	mpll: clock-mpll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "mpll";
+		#clock-cells = <0>;
+	};
+
+	ahbbridge0: bus at 40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40000000 0x800000>;
+		ranges;
+
+		lpuart4: serial at 402d0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402d0000 0x1000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+			assigned-clock-rates = <24000000>;
+			status = "disabled";
+		};
+
+		lpuart5: serial at 402e0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402e0000 0x1000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		tpm5: tpm at 40260000 {
+			compatible = "fsl,imx7ulp-tpm";
+			reg = <0x40260000 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			clock-names = "ipg", "per";
+		};
+
+		usdhc0: mmc at 40370000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40370000 0x10000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC0>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		usdhc1: mmc at 40380000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40380000 0x10000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC1>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		scg1: clock-controller at 403e0000 {
+			compatible = "fsl,imx7ulp-scg1";
+			reg = <0x403e0000 0x10000>;
+			clocks = <&rosc>, <&sosc>, <&sirc>,
+				 <&firc>, <&upll>, <&mpll>;
+			clock-names = "rosc", "sosc", "sirc",
+				      "firc", "upll", "mpll";
+			#clock-cells = <1>;
+		};
+
+		pcc2: clock-controller at 403f0000 {
+			compatible = "fsl,imx7ulp-pcc2";
+			reg = <0x403f0000 0x10000>;
+			#clock-cells = <1>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
+				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+				 <&scg1 IMX7ULP_CLK_UPLL>,
+				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
+				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+				 <&scg1 IMX7ULP_CLK_ROSC>,
+				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
+				      "upll", "sosc_bus_clk", "mpll",
+				      "firc_bus_clk", "rosc", "spll_bus_clk";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+		};
+
+		smc1: smc1 at 40410000 {
+			compatible = "fsl,imx7ulp-smc1";
+			reg = <0x40410000 0x1000>;
+		};
+
+		pcc3: clock-controller at 40b30000 {
+			compatible = "fsl,imx7ulp-pcc3";
+			reg = <0x40b30000 0x10000>;
+			#clock-cells = <1>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
+				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+				 <&scg1 IMX7ULP_CLK_UPLL>,
+				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
+				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+				 <&scg1 IMX7ULP_CLK_ROSC>,
+				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
+				      "upll", "sosc_bus_clk", "mpll",
+				      "firc_bus_clk", "rosc", "spll_bus_clk";
+		};
+	};
+
+	ahbbridge1: bus at 40800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40800000 0x800000>;
+		ranges;
+
+		lpi2c6: i2c at 40a40000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a40000 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpi2c7: i2c at 40a50000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a50000 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart6: serial at 40a60000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a60000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart7: serial at 40a70000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a70000 0x1000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		iomuxc1: pinctrl at 40ac0000 {
+			compatible = "fsl,imx7ulp-iomuxc1";
+			reg = <0x40ac0000 0x1000>;
+		};
+
+		gpio_ptc: gpio at 40ae0000 {
+			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLC>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 0 32>;
+		};
+
+		gpio_ptd: gpio at 40af0000 {
+			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLD>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 32 32>;
+		};
+
+		gpio_pte: gpio at 40b00000 {
+			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 64 32>;
+		};
+
+		gpio_ptf: gpio at 40b10000 {
+			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLF>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 96 32>;
+		};
+	};
+};
-- 
2.7.4

[PATCH V5 5/6] dts: fsl: add imx7ulp evk support

[A.s. Dong]

The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MX 7ULP, which features NXP's advanced implementation
of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and
2D Graphics Processing Units (GPUs).

The EVK enables HDMI output for simple out-of-the-box to bring up but
allows reconfiguration for MIPI displays. The EVK is designed as a
System-On-Module(SOM) board that connects to an associated baseboard.
The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card
socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector
and an NXP PF1550 power management IC (PMIC). The baseboard provides
additional capabilities including a full SD/MMC 3.0 card socket, audio
codec, multiple sensors, an HDMI connector, and an alternate MIPI display
connector. Additionally, the EVK facilitates software development with the
ultimate goal of faster time to market through the support of both
Linux OS and AndroidTM rich operating systems, as well as FreeRTOS.

This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
FEC
SD/MMC

See more board details:
https://www.nxp.com/products/processors-and-microcontrollers/
arm-based-processors-and-mcus/i.mx-applications-processors/
i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications
-processor:MCIMX7ULP-EVK

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v4->v5:
 * update pad setting due to missing pull up enabled
   (formerly auto done by driver generic pinconfg)
v3->v4:
 * no changes
v2->v3:
 * remove "Generic DT based system"
 * add device_type property for memory node
 * back to old pinctrl binding according to SoC maintainer's suggestions
v1->v2:
 * switch to SPDX license
 * pad name update
 * fix Character '_' not recommended in node name
 * separate from soc.dtsi file
---
 arch/arm/boot/dts/Makefile        |  2 +
 arch/arm/boot/dts/imx7ulp-evk.dts | 77 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d7268ae..39eac9c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,6 +573,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-moxa-uc-8410a.dtb \
 	ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..a09026a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory at 60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		fsl,pins = <
+			IMX7ULP_PAD_PTC3__LPUART4_RX	0x3
+			IMX7ULP_PAD_PTC2__LPUART4_TX	0x3
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0: usdhc0grp {
+		fsl,pins = <
+			IMX7ULP_PAD_PTD1__SDHC0_CMD	0x43
+			IMX7ULP_PAD_PTD2__SDHC0_CLK	0x40
+			IMX7ULP_PAD_PTD7__SDHC0_D3	0x43
+			IMX7ULP_PAD_PTD8__SDHC0_D2	0x43
+			IMX7ULP_PAD_PTD9__SDHC0_D1	0x43
+			IMX7ULP_PAD_PTD10__SDHC0_D0	0x43
+			IMX7ULP_PAD_PTC10__PTC10	0x3	/* CD */
+		>;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
+		fsl,pins = <
+			IMX7ULP_PAD_PTD0__PTD0		0x3
+		>;
+	};
+};
-- 
2.7.4

[PATCH V5 6/6] ARM: imx_v6_v7_defconfig: add imx7ulp support

[A.s. Dong]

Select CONFIG_SOC_IMX7ULP by default.
Patch generated via make ARCH=arm savedefconfig

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v2->v3:
 * no changes
v1->v2:
 * rebase to new version
---
 arch/arm/configs/imx_v6_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 1ad5736..27ee422 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -38,6 +38,7 @@ CONFIG_SOC_IMX6SLL=y
 CONFIG_SOC_IMX6SX=y
 CONFIG_SOC_IMX6UL=y
 CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
 CONFIG_SOC_VF610=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
-- 
2.7.4

[PATCH V5 1/6] dt-bindings: fsl: add compatible for imx7ulp evk

[Fabio Estevam]

On Sat, Nov 10, 2018 at 1:13 PM A.s. Dong <aisheng.dong@nxp.com> wrote:

Even a single line commit log would be better here.

> Cc: devicetree at vger.kernel.org
> Cc: Shawn Guo <shawnguo@kernel.org>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[PATCH V5 2/6] dt-bindings: fsl: add imx7ulp pm related components bindings

[Fabio Estevam]

On Sat, Nov 10, 2018 at 1:13 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
>
> Add imx7ulp pm related components bindings
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree at vger.kernel.org
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[PATCH V5 3/6] ARM: imx: add initial support for imx7ulp

[Fabio Estevam]

On Sat, Nov 10, 2018 at 1:14 PM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +static void __init imx7ulp_init_machine(void)
> +{
> +       imx7ulp_pm_init();
> +
> +       mxc_set_cpu_type(MXC_CPU_IMX7ULP);
> +       /* FIXME: so far there is still no way to retrieve SoC version */
> +       imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_UNKNOWN);

Then maybe just do not call imx_print_silicon_rev() for now?

Anyway:

Reviewed-by: Fabio Estevam <festevam@gmail.com>

[PATCH V5 4/6] dts: imx: add common imx7ulp dtsi support

[Fabio Estevam]

On Sat, Nov 10, 2018 at 1:13 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
>
> The i.MX 7ULP family of processors features NXP's advanced implementation
> of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
> Graphics Processing Units (GPUs).
>
> This patch aims to add the initial support including:
> 1) CLK
> 2) GPIO PTC, PTD, PTE, PTF
> 3) uSDHC 1/2
> 4) LPUART 4/5/6/7
> 5) LPI2C 6/7
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>

RE: [PATCH V5 0/6] ARM: imx: add imx7ulp support

[Aisheng DONG]

Hi Shawn,

Can you help pick up imx7ulp support series?
The clk patch set is already in clk tree now.
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/log/?h=clk-imx7ulp

Please let me know if you need me to resend.

Regards
Dong Aisheng

> -----Original Message-----
> From: A.s. Dong
> Sent: Saturday, November 10, 2018 11:13 PM
> To: linux-arm-kernel@lists.infradead.org
> Cc: dongas86@gmail.com; kernel@pengutronix.de; shawnguo@kernel.org;
> Fabio Estevam <fabio.estevam@nxp.com>; robh+dt@kernel.org; dl-linux-imx
> <linux-imx@nxp.com>; linux@armlinux.org.uk; A.s. Dong
> <aisheng.dong@nxp.com>
> Subject: [PATCH V5 0/6] ARM: imx: add imx7ulp support
> 
> The i.MX 7ULP family of processors represents NXP’s latest achievement in
> ultra-low-power processing for use cases demanding long battery life.
> Targeted towards the growing market of portable devices, the i.MX 7ULP
> family of processors features NXP's advanced implementation of the Arm®
> Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
> Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit
> LPDDR2/LPDDR3 memory interface and a number of other interfaces for
> connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera
> sensors.
> 
> This patch series adds the basic support for imx7ulp. It includes machine level
> support code and device tree.
> Note: it depends on clk driver which is still under review.
> 
> v4->v5:
>  * dts add input clocks for PCC module
>  * update pad setting due to missing pull up enabled
>    (formerly auto done by driver generic pinconfg)
>  * gpio and pinctrl patches were merged by Linus W, so dropped in this series
>   dt-bindings: gpio: vf610: add optional clocks property
>   gpio: vf610: add optional clock support
>   dt-bindings: pinctrl: imx7ulp: back to imx legacy binding for
>     consistency
>   pinctrl: fsl: imx7ulp: change to use imx legacy binding
> 
> v3->v4:
>  * add comments about fixed soc version
>  * add iounmap
> v2->v3:
>  * back to old pinctrl binding according to SoC maintainer's suggestions
>  * use generic node name
>  * error checking updated according to Russell's suggestion:
>    ptr == ERR_PTR(-EPROBE_DEFER)
> 
> v1->v2:
>  * switch to SPDX license
>  * rebase to latest tree
>  * pad name update
>  * add gpio clk support
>  * minor fix
> 
> 
> 
> Dong Aisheng (6):
>   dt-bindings: fsl: add compatible for imx7ulp evk
>   dt-bindings: fsl: add imx7ulp pm related components bindings
>   ARM: imx: add initial support for imx7ulp
>   dts: imx: add common imx7ulp dtsi support
>   dts: fsl: add imx7ulp evk support
>   ARM: imx_v6_v7_defconfig: add imx7ulp support
> 
>  .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      |  23 ++
>  Documentation/devicetree/bindings/arm/fsl.txt      |   8 +
>  arch/arm/boot/dts/Makefile                         |   2 +
>  arch/arm/boot/dts/imx7ulp-evk.dts                  |  77 +++++
>  arch/arm/boot/dts/imx7ulp.dtsi                     | 346
> +++++++++++++++++++++
>  arch/arm/configs/imx_v6_v7_defconfig               |   1 +
>  arch/arm/mach-imx/Kconfig                          |   9 +
>  arch/arm/mach-imx/Makefile                         |   1 +
>  arch/arm/mach-imx/common.h                         |   1 +
>  arch/arm/mach-imx/cpu.c                            |   3 +
>  arch/arm/mach-imx/mach-imx7ulp.c                   |  33 ++
>  arch/arm/mach-imx/mxc.h                            |   1 +
>  arch/arm/mach-imx/pm-imx7ulp.c                     |  29 ++
>  13 files changed, 534 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
>  create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts  create mode
> 100644 arch/arm/boot/dts/imx7ulp.dtsi  create mode 100644
> arch/arm/mach-imx/mach-imx7ulp.c  create mode 100644
> arch/arm/mach-imx/pm-imx7ulp.c
> 
> --
> 2.7.4

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Re: [PATCH V5 1/6] dt-bindings: fsl: add compatible for imx7ulp evk

[Shawn Guo]

On Sat, Nov 10, 2018 at 01:50:13PM -0200, Fabio Estevam wrote:
> On Sat, Nov 10, 2018 at 1:13 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> Even a single line commit log would be better here.

+1

I added a simple commit log and applied the patch.

Shawn

> 
> > Cc: devicetree@vger.kernel.org
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Acked-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> Reviewed-by: Fabio Estevam <festevam@gmail.com>

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Re: [PATCH V5 2/6] dt-bindings: fsl: add imx7ulp pm related components bindings

[Shawn Guo]

On Sat, Nov 10, 2018 at 03:13:00PM +0000, A.s. Dong wrote:
> Add imx7ulp pm related components bindings
> 
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Applied, thanks.

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Re: [PATCH V5 3/6] ARM: imx: add initial support for imx7ulp

[Shawn Guo]

On Sat, Nov 10, 2018 at 01:51:57PM -0200, Fabio Estevam wrote:
> On Sat, Nov 10, 2018 at 1:14 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +static void __init imx7ulp_init_machine(void)
> > +{
> > +       imx7ulp_pm_init();
> > +
> > +       mxc_set_cpu_type(MXC_CPU_IMX7ULP);
> > +       /* FIXME: so far there is still no way to retrieve SoC version */
> > +       imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_UNKNOWN);
> 
> Then maybe just do not call imx_print_silicon_rev() for now?

I'm with Fabio on this.  Applied the patch by dropping the call and
FIXME comment above.

Shawn

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Re: [PATCH V5 4/6] dts: imx: add common imx7ulp dtsi support

[Shawn Guo]

On Sat, Nov 10, 2018 at 03:13:08PM +0000, A.s. Dong wrote:
> The i.MX 7ULP family of processors features NXP's advanced implementation
> of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
> Graphics Processing Units (GPUs).
> 
> This patch aims to add the initial support including:
> 1) CLK
> 2) GPIO PTC, PTD, PTE, PTF
> 3) uSDHC 1/2
> 4) LPUART 4/5/6/7
> 5) LPI2C 6/7
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Changed the subject prefix like 'ARM: dts: imx: ...', and applied the
patch.

Shawn

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Re: [PATCH V5 5/6] dts: fsl: add imx7ulp evk support

[Shawn Guo]

On Sat, Nov 10, 2018 at 03:13:12PM +0000, A.s. Dong wrote:
> The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid
> evaluation of the i.MX 7ULP, which features NXP's advanced implementation
> of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and
> 2D Graphics Processing Units (GPUs).
> 
> The EVK enables HDMI output for simple out-of-the-box to bring up but
> allows reconfiguration for MIPI displays. The EVK is designed as a
> System-On-Module(SOM) board that connects to an associated baseboard.
> The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card
> socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector
> and an NXP PF1550 power management IC (PMIC). The baseboard provides
> additional capabilities including a full SD/MMC 3.0 card socket, audio
> codec, multiple sensors, an HDMI connector, and an alternate MIPI display
> connector. Additionally, the EVK facilitates software development with the
> ultimate goal of faster time to market through the support of both
> Linux OS and AndroidTM rich operating systems, as well as FreeRTOS.
> 
> This patch aims to support the preliminary booting up features
> as follows:
> GPIO
> LPUART
> FEC
> SD/MMC
> 
> See more board details:
> https://www.nxp.com/products/processors-and-microcontrollers/
> arm-based-processors-and-mcus/i.mx-applications-processors/
> i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications
> -processor:MCIMX7ULP-EVK
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Changed the subject prefix like 'ARM: dts: imx: ...', and applied the
patch.

Shawn

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Re: [PATCH V5 6/6] ARM: imx_v6_v7_defconfig: add imx7ulp support

[Shawn Guo]

On Sat, Nov 10, 2018 at 03:13:16PM +0000, A.s. Dong wrote:
> Select CONFIG_SOC_IMX7ULP by default.
> Patch generated via make ARCH=arm savedefconfig
> 
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

Applied, thanks.

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