Re: [PATCH 0/2] pinctrl: sunxi: Account for per-bank GPIO regulators

Chen-Yu Tsai
2018-12-06T15:28:52Z

On Thu, Dec 6, 2018 at 10:02 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> Hi,
>
> Here is a first attempt at getting the regulators properly accounted for
> the GPIO banks on the Allwinner SoCs.

Cool. This is better than what I had in mind, which involved a deferred
task to grab the regulators.

> The main interogation I have currently is whether we should always try to
> get the regulator for the current branch, or if we should restrict it to
> the one available on the SoCs.

Not sure what you mean here, but we should probably just list the actual
names.

For pre-A20 SoCs (A10/A10s/A13), they aren't even named VCC-Px. Instead
they are named after the primary function of the pin bank, such as
VCC-CARD, VCC-NAND, VCC-CSI0, VCC-CSI1.

For pin banks that don't have per-bank power inputs, you should fall back
to VCC-IO, or VCC-RTC in the case of the PL pins.

So here's the rub: On A33 and later SoCs that are paired with a PMIC, VCC-PL
or VCC-RTC is powered by the RTC regulator of the PMIC, which only gets
registered when the PMIC regulator driver is probed, which needs the RSB
controller, which needs the pin controller and the PL pins...

ChenYu

>
> Let me know what you think,
> Maxime
>
> Maxime Ripard (2):
> pinctrl: sunxi: Deal with per-bank regulators
> ARM: dts: sun7i: bananapi: Add GPIO banks regulators
>
> arch/arm/boot/dts/sun7i-a20-bananapi.dts | 5 ++-
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 63 +++++++++++++++++++++++++-
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 6 ++-
> 3 files changed, 74 insertions(+)
>
> base-commit: 651022382c7f8da46cb4872a545ee1da6d097d2a
> --
> git-series 0.9.1