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Received: from foss.arm.com ([217.140.101.70]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gVKJM-00044i-FN for linux-arm-kernel@lists.infradead.org; Fri, 07 Dec 2018 17:53:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB68A165C; Fri, 7 Dec 2018 09:53:09 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9B9BE3F5AF; Fri, 7 Dec 2018 09:53:09 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 21FFC1AE0BA4; Fri, 7 Dec 2018 17:53:31 +0000 (GMT) Date: Fri, 7 Dec 2018 17:53:31 +0000 From: Will Deacon To: Alexander Van Brunt Subject: Re: [PATCH V3] arm64: Don't flush tlb while clearing the accessed bit Message-ID: <20181207175330.GC11430@edgewater-inn.cambridge.arm.com> References: <1540805158-618-1-git-send-email-amhetre@nvidia.com> <20181029105515.GD14127@arm.com> <20181206191850.GC20796@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+30 (d10eec459b35) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181207_175312_659849_2A2BD123 X-CRM114-Status: GOOD ( 25.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "linux-kernel@vger.kernel.org" , Sachin Nikam , "linux-tegra@vger.kernel.org" , Ashish Mhetre , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 06, 2018 at 08:42:03PM +0000, Alexander Van Brunt wrote: > > > >=A0If we roll a TLB invalidation routine without the trailing DSB, w= hat sort of > > > >=A0performance does that get you? > > > = > > > It is not as good. In some cases, it is really bad. Skipping the inva= lidate was > > > the most consistent and fast implementation. > = > > My problem with that is it's not really much different to just skipping= the > > page table update entirely. Skipping the DSB is closer to what is done = on > > x86, where we bound the stale entry time to the next context-switch. > = > Which of the three implementations is the "that" and "it" in the first se= ntence? that =3D it =3D skipping the whole invalidation + the DSB > > Given that I already queued the version without the DSB, we have the ch= oice > > to either continue with that or to revert it and go back to the previous > >=A0behaviour. Which would you prefer? > = > To me, skipping the DSB is a win over doing the invalidate and the DSB be= cause > it is faster on average. > = > DSBs have a big impact on the performance of other CPUs in the inner shar= eable > domain because of the ordering requirements. For example, we have observed > Cortex A57s stalling all CPUs in the cluster until Device accesses comple= te. > = > Would you be open to a patch on top of the DSB skipping patch that skips = the > whole invalidate? I don't think so; we don't have an upper bound on how long we'll have a stale TLB if remove the invalidation completely. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel