From: Christoffer Dall <christoffer.dall@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
James Morse <james.morse@arm.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/8] arm64: KVM: Make VHE Stage-2 TLB invalidation operations non-interruptible
Date: Mon, 10 Dec 2018 11:03:56 +0100 [thread overview]
Message-ID: <20181210100356.GG30263@e113682-lin.lund.arm.com> (raw)
In-Reply-To: <20181206173126.139877-2-marc.zyngier@arm.com>
On Thu, Dec 06, 2018 at 05:31:19PM +0000, Marc Zyngier wrote:
> Contrary to the non-VHE version of the TLB invalidation helpers, the VHE
> code has interrupts enabled, meaning that we can take an interrupt in
> the middle of such a sequence, and start running something else with
> HCR_EL2.TGE cleared.
Do we have to clear TGE to perform the TLB invalidation, or is that just
a side-effect of re-using code?
Also, do we generally perform TLB invalidations in the kernel with
interrupts disabled, or is this just a result of clearing TGE?
Somehow I feel like this should look more like just another TLB
invalidation in the kernel, but if there's a good reason why it can't
then this is fine.
Thanks,
Christoffer
>
> That's really not a good idea.
>
> Take the heavy-handed option and disable interrupts in
> __tlb_switch_to_guest_vhe, restoring them in __tlb_switch_to_host_vhe.
> The latter also gain an ISB in order to make sure that TGE really has
> taken effect.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm64/kvm/hyp/tlb.c | 35 +++++++++++++++++++++++++----------
> 1 file changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
> index 4dbd9c69a96d..7fcc9c1a5f45 100644
> --- a/arch/arm64/kvm/hyp/tlb.c
> +++ b/arch/arm64/kvm/hyp/tlb.c
> @@ -15,14 +15,19 @@
> * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#include <linux/irqflags.h>
> +
> #include <asm/kvm_hyp.h>
> #include <asm/kvm_mmu.h>
> #include <asm/tlbflush.h>
>
> -static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm)
> +static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm,
> + unsigned long *flags)
> {
> u64 val;
>
> + local_irq_save(*flags);
> +
> /*
> * With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and
> * most TLB operations target EL2/EL0. In order to affect the
> @@ -37,7 +42,8 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm)
> isb();
> }
>
> -static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm)
> +static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm,
> + unsigned long *flags)
> {
> __load_guest_stage2(kvm);
> isb();
> @@ -48,7 +54,8 @@ static hyp_alternate_select(__tlb_switch_to_guest,
> __tlb_switch_to_guest_vhe,
> ARM64_HAS_VIRT_HOST_EXTN);
>
> -static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm)
> +static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm,
> + unsigned long flags)
> {
> /*
> * We're done with the TLB operation, let's restore the host's
> @@ -56,9 +63,12 @@ static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm)
> */
> write_sysreg(0, vttbr_el2);
> write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
> + isb();
> + local_irq_restore(flags);
> }
>
> -static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm)
> +static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm,
> + unsigned long flags)
> {
> write_sysreg(0, vttbr_el2);
> }
> @@ -70,11 +80,13 @@ static hyp_alternate_select(__tlb_switch_to_host,
>
> void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
> {
> + unsigned long flags;
> +
> dsb(ishst);
>
> /* Switch to requested VMID */
> kvm = kern_hyp_va(kvm);
> - __tlb_switch_to_guest()(kvm);
> + __tlb_switch_to_guest()(kvm, &flags);
>
> /*
> * We could do so much better if we had the VA as well.
> @@ -117,36 +129,39 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
> if (!has_vhe() && icache_is_vpipt())
> __flush_icache_all();
>
> - __tlb_switch_to_host()(kvm);
> + __tlb_switch_to_host()(kvm, flags);
> }
>
> void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
> {
> + unsigned long flags;
> +
> dsb(ishst);
>
> /* Switch to requested VMID */
> kvm = kern_hyp_va(kvm);
> - __tlb_switch_to_guest()(kvm);
> + __tlb_switch_to_guest()(kvm, &flags);
>
> __tlbi(vmalls12e1is);
> dsb(ish);
> isb();
>
> - __tlb_switch_to_host()(kvm);
> + __tlb_switch_to_host()(kvm, flags);
> }
>
> void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
> {
> struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
> + unsigned long flags;
>
> /* Switch to requested VMID */
> - __tlb_switch_to_guest()(kvm);
> + __tlb_switch_to_guest()(kvm, &flags);
>
> __tlbi(vmalle1);
> dsb(nsh);
> isb();
>
> - __tlb_switch_to_host()(kvm);
> + __tlb_switch_to_host()(kvm, flags);
> }
>
> void __hyp_text __kvm_flush_vm_context(void)
> --
> 2.19.2
>
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next prev parent reply other threads:[~2018-12-10 10:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-06 17:31 [PATCH v3 0/8] Workaround for Cortex-A76 erratum 1165522 Marc Zyngier
2018-12-06 17:31 ` [PATCH v3 1/8] arm64: KVM: Make VHE Stage-2 TLB invalidation operations non-interruptible Marc Zyngier
2018-12-10 10:03 ` Christoffer Dall [this message]
2018-12-10 10:24 ` Marc Zyngier
2018-12-10 10:49 ` Christoffer Dall
2018-12-06 17:31 ` [PATCH v3 2/8] KVM: arm64: Rework detection of SVE, !VHE systems Marc Zyngier
2018-12-10 10:13 ` Christoffer Dall
2018-12-10 10:28 ` Marc Zyngier
2018-12-10 12:40 ` Will Deacon
2018-12-06 17:31 ` [PATCH v3 3/8] arm64: KVM: Install stage-2 translation before enabling traps Marc Zyngier
2018-12-10 10:13 ` Christoffer Dall
2018-12-06 17:31 ` [PATCH v3 4/8] arm64: Add TCR_EPD{0,1} definitions Marc Zyngier
2018-12-06 17:31 ` [PATCH v3 5/8] arm64: KVM: Force VHE for systems affected by erratum 1165522 Marc Zyngier
2018-12-06 17:31 ` [PATCH v3 6/8] arm64: KVM: Add synchronization on translation regime change for " Marc Zyngier
2018-12-10 10:15 ` Christoffer Dall
2018-12-06 17:31 ` [PATCH v3 7/8] arm64: KVM: Handle ARM erratum 1165522 in TLB invalidation Marc Zyngier
2018-12-10 10:19 ` Christoffer Dall
2018-12-10 10:46 ` Marc Zyngier
2018-12-10 11:15 ` James Morse
2018-12-10 11:50 ` Christoffer Dall
2018-12-06 17:31 ` [PATCH v3 8/8] arm64: Add configuration/documentation for Cortex-A76 erratum 1165522 Marc Zyngier
2018-12-07 11:09 ` [PATCH v3 0/8] Workaround " James Morse
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