From: Russell King - ARM Linux <linux@armlinux.org.uk>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: mm: skip cleaning of idmap page tables on LPAE capable cores
Date: Mon, 10 Dec 2018 15:48:09 +0000 [thread overview]
Message-ID: <20181210154808.GF30658@n2100.armlinux.org.uk> (raw)
In-Reply-To: <20181210152855.3634-1-ard.biesheuvel@linaro.org>
On Mon, Dec 10, 2018 at 04:28:55PM +0100, Ard Biesheuvel wrote:
> Since only LPAE capable CPUs may execute under virtualization, and
> considering that LPAE capable CPUs are guaranteed to have cache
> coherent page table walkers (per the architecture), let's only
> perform this cache maintenance on non-LPAE cores.
That statement doesn't stack up. What about Cortex A15, which is a
32-bit core with LPAE support? TI Keystone2 SoCs fall into this
category.
Sorry, but no, I don't think we can omit this cache flush on LPAE.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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next prev parent reply other threads:[~2018-12-10 15:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-10 15:28 [PATCH] ARM: mm: skip cleaning of idmap page tables on LPAE capable cores Ard Biesheuvel
2018-12-10 15:48 ` Russell King - ARM Linux [this message]
2018-12-10 16:13 ` Marc Zyngier
2018-12-13 10:57 ` Ard Biesheuvel
2018-12-13 11:40 ` Marc Zyngier
2018-12-13 11:42 ` Ard Biesheuvel
2018-12-13 12:00 ` Marc Zyngier
2018-12-13 12:03 ` Marc Zyngier
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